This video talks about advantages and design challenges of fully on chip LDOs. Fully on chip, Miller compensated PMOS LDOs are discussed. Challenges in frequency compensation and fast transient response are discussed.
Thanks for your video. Have a few points:- -You can have nF of cap and make output pole dominant through on chip MIM capacitor. Output cap of the order of 100s of pF cant sustain much load transient. -Miller compensation makes PSRR really bad a very important spec for LDO. I don't think this topology sports a worst case PSRR any better an -10 to -15dB.
Thanks for your inputs. Yes, good points. PSR is especially a nagging issue with Miller compensated LDOs. One solution can be adding additional loops to improve it.
Hello Sir, very helpful video. I am presently designing an FVF structure to support fast transients. Looking forward to hear your thoughts on that 😊. It will be helpful if you could touch on the stability analysis of such dual loops. Eagerly waiting to look at FVF structures from your point of view and learn more.
