9:10 디지털회로 > FF> Logic gates(and,or,nand,,,) > 트랜지스터 즉 디지털회로는 수십수백억의 T로 이뤄지기 때문에, T레벨에서 설계하면 설계 속도가 너무 느림 T레벨의 정보를 감추기위해 더 상위레벨인 Register 레벨에서 설계하는 RTL 을 HDL을 이용해서 수행함
Hi Sir , I have a question about referencing signals within a clocking block which itself is part of modport . Consider following snippet :: interface mult_if (input logic clk, reset); logic [7:0] a, b; logic [15:0] out; logic en; logic ack; clocking cb @(posedge clk); default input #1 output #2; input out, ack; output a,b, en; endclocking modport TB (clocking cb, input clk, reset); modport RTL (input clk, reset, a,b, en, output out, ack); endinterface Assume ' mult_if ' is instantiated in top_tb and then set in config_db to be fetched via driver and monitor . Within monitor , how should I reference output signals ' a ' / ' b ' / ' en ' Should it be :: vif_intf.TB.cb.a OR vif_intf.cb.a ? I observe only VCS throws an error when using vif_intf.TB.cb.a whereas all the 3 tools are fine with vif_intf.cb.a Thanks in advance .
The site is still available in systemverilogacademy.com , but this specific course (or the course link) is not available after we upgraded the site. Will try to resurrect its asap, sorry about that.
The specification are documented like any other 'document' 🙂. It could be as simple as a written word or mostly some form of a webpage, which can be processed by scripts to exact data that need to be used in verification.
