An Introduction to Verilog 

This short 5 minute video is the best available on verilog

The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!

Pretty intuitive, this should be the best Verilog introduction video ever.

I have been searching for this exact video for three days you are an absolute lifesaver thank you

Very well organized! This is the most coherent description I've found. Thanks!

This video is the BEST way to understand a whole frickin topic in 5 mins. Literally the best video for beginners

excellent. absolutely excellent! Love the simplicity in the explanartion and the straight fordwardness

even though it isn't a programming language, it is very similar to object oriented languages class -> module wire -> variable module adder(o,x,y) -> constructor this is very similar to c++. your explanation is amazing!! thanks for putting in so much effort

Excellent explanation thanx

Sir, thank you so much! Your video was not only helpful but gave me an excellent start to my verilog learning experience.

One of the best video got so far, clear, crisp..

Shortest, simplest and best explanation on Verilog!

Excellent video ! I been trying to learn verilog for a while and this really helped me understand it better.

The quickest video to understand what the Verilog is. Thx.

RESPECT BROTHER !!! 4 min video>>>>prof's 1 hour lecture

Best introduction to Verilog! Previously I was thinking that it is a programming language.

This video refers to structural hardware description, but hardware description languages also provide rtl description

This video will definitely save my test *peace*

You sir a amazing! I thought they only taught VHDL in the midwest, but I guess I'm wrong.

the best video about Verilog, the vlogger is smart for sure.

even after years still the best. bless your soul

The best verilog tutorial I ever seen :)

awesome 5 minutes of my life searching here and there for verilog basics

Simple and Sweet. Thanks for the informative video☺

Thank you so much it simplifies the core of understanding Verilog with in 5 minutes👏

This is the best organized video........take love

Very well explained. Thank you. Can you make more ruboost tutorial about Verilog.

Simple and straight forward! Thank you!

Sir your explanation is best you should must make more videos on verilog as well as system verilog and UVM

You know what RU-vid, next time put this video as the first suggestion for Verilog. Not some company videos nobody will easily understand.

best video i found for verilog. More please

why are you stopped making videos on verilogs, its so nice with great and relateble examples

This video is the best video about verilog which i understood clearly.

Amazing Video ! Btw, Really shocked when i knew that Verilog does not describe bedrooms :"D

Simple and on the point! Best explanation

great start, I wish there was a full course

you're a legend mate

This is the best short video for verilog basic

Sir I am beginner simple study and systematic way cleary explain.thanks lot

Been reading websites about Verilog. Why can't websites explain any clearer like your videos. Thanks!

Beautiful !!! The world needs more FPGAs

amazing, love the quick bite info style tysm

Wow this was super helpful!!! Thank god i got to this before my exams came up

It's like PLC languages when they were more basic than they are now. My favorite since I was trained using S7 with LOGO!, a Click and Drag Logic Gates and Compile, is FBD (Function Block Diagram). How far am I from machine code or is it really not so advanced for stability’s sake? In that regard, my favorite quote is : "If I would deliver code like the folks from windows do, I would lose my job immediately"

as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.

THANK YOU! The visual aids helped alot!

Thanks for solving my doubts about verilog

Very concise and clear description!

Amazingly concise and so beginner-friendly

😂😂I watched 4 videos on verilog ,and this single video explained content of those 4 videos. Superb explanation.

Oh my God. Thank you. Seriously

Thanks ! Your explanation was clear !

very easier beginning for learner. thankyou sir...

that was great !, dont u have a playlist on verilog coding /xilinx ??

Exceptionally good intro. Nicely done.

waw...superb teaching technique....thank u

Very good introduction, thanks. It somewhat begs the questions "wires?". Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another? Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module? Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs? Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.

Awesome!!! Thanks a bunch!!!

Amazing Video Sir! Kindly make such a video on VHDL

Great video, I learned more about verilog!

Best Video Ever U seen About Iverilog

Thank you for your simple and understandable video.

Wow, now I understand what Verilog actually is, thanx!

Best video for beginners.

You just crushed it bro.

it tok me exactly 5 mins to understand . nice job

plz make more videos..

Thank you so much . You are awesome!!!

Thanks! Excellent explanation.

Woah man! Thank you so much!!! 😊 Really appreciate your efforts!

Excellent bro.. ❤️👑

Great short description of Verilog

sir plzz make A playlist on complete verilog or plzz suggest a book for verilog

superb video thank you thank you thank you so so much :D

Okay, this was amazing. Thank you

Very good introduction to Verilog !

such a great explanation, thank you

Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.

Really wonderful expanation ..

Excellent video

extremely well explained. Thank you sir :)

impressive and informative!

Nice video, do more

Very well presented ...

Fantastic, thank you!

amazing video

This is amazing!

So nice thanks

My bad - I started first with VHDL, then discovered that Verilog is easier. Yet, somehow I like more VHDL than Verilog. I can't understand myself.

this is awesome... sir

can we use assign statement? for example assign or_wire= x|y ; assign not_wire= ~y ; assign o=or_wire & not_wire ;

damn! how much clearer can you get??

excellent...

this 4 min video is better than intel's 50 min video.

Awesome

Thanks, It was very clear.

Best video for verilog

really cool video, thanks :D

very good, thanks

Best video ever