The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!
even though it isn't a programming language, it is very similar to object oriented languages class -> module wire -> variable module adder(o,x,y) -> constructor this is very similar to c++. your explanation is amazing!! thanks for putting in so much effort
It's like PLC languages when they were more basic than they are now. My favorite since I was trained using S7 with LOGO!, a Click and Drag Logic Gates and Compile, is FBD (Function Block Diagram). How far am I from machine code or is it really not so advanced for stability’s sake? In that regard, my favorite quote is : "If I would deliver code like the folks from windows do, I would lose my job immediately"
as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.
Very good introduction, thanks. It somewhat begs the questions "wires?". Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another? Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module? Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs? Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.
Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.