Blocking or non-blocking assignments can give you either combinational or sequential logic depending on the sensitivity list of the always block these assignments are included in.
At 4:02 I don't understand why the data flow is out1 = ((~X&A)&A)|(B&X); isn't the second &A redundant? I would think assign out1 = (~X&A)|(X&B); ? I haven't tried it in a tool so don't know if there is another reason to construct the statement this way. Great Video. Thanks.
Very goog. Short sweet and to the point! Your explanation of blocking and non-blocking was especially good. Coming from a programming background I get wrapped around that axel constantly.
00:01 Verilog coding involves three different layers of abstraction and understanding the difference between combinational and sequential logic is important. 01:59 Modeling in Verilog at the gate level involves instantiating each logic gate independently and connecting them together using wires. 03:46 Behavioral level Verilog code describes circuit behavior at a high abstraction level. 05:40 Multiplexer can be implemented in different ways: gate level, data flow level, and behavioral level. 07:31 Utilize D-type flip-flops for sequential logic 09:14 Blocking and non-blocking assignments have different evaluation and assignment processes. 11:03 Understanding the difference between blocking and non-blocking assignments in Verilog 12:54 Use blocking assignments for combinational logic and non-blocking assignments for sequential logic.
You can remove left internal parentheses without any effect. Then you can see that A & A is always equals A. So your two expressions are the same. There definitely is a rule of the formal logic that describes this kind of cases but I'm to lazy to take the book from the shelf.)
I don't have any background in this subject, but I want to know why, at the data flow level, he used `((~X & A) & A) | (X & B)` and not `(~X & A) | (X & B)`.
It's a trick! Were you paying attention? Is your compiler a piece of s...? (it emit a warning "statement has no effect". at best it'll optimize it out.)
How do codes written at these different level of abstractions convert to synthesis in ASIC Design? Say I write, assign wire = (a&b) | (c&d) ; I can come up with 3 possible ways to synthesize this: 1) 2 AND, 1 OR gate ( 18 Transistors ) 2) 3 NAND gates ( 12 Transistors ) 3) AND-OR22 module ( 10 Transistors ) Which one does the code synthesize in this case and how does it make that decision?
I'd assume number 1, because that is the literal interpretation of the boolean expression. Unless the synthesizer has a way to automatically simplify boolean expressions into simpler circuits.
Thks &; I'm new to FPGAs & will try to watch your whole playlist. Oh a question, I would like to program FPGAs via smartphone & I hope to use the smartphone as the human interface to the FPGA. ??Can you point me in the right direction to get started??
Hi, thanks! I'm not aware of any development tool or existing project which does this. Programming the FPGA is not a simple task so it will be a big challenge!
@@VisualElectric_ Thks, a few more newbie questions though; I been researching FPGAs (how they work in theory) & collecting the material to come up to speed. Now I need to choice my 1st FPGA to learn-on. 1. Given the initial comment, ??Which FPGA would you recommend to try implementing all these crux FPGA theories (ex: LUTs, Boolean Algebra, SOP/POS tables, etc) I've learnt so I can minimize frustration, profanity, throwing-things, etc ;)?? 2. ??What are some good groups/resources/etc to learn FPGAs with others knowledgeable people?? (I've found slim-to-none except a few good but old books, RU-vid playlists, etc ;) 3. ??Why pray-tell ain't FPGAs more popular?? (ex: programable FPGA hardware, parallel FPGA processing, etc runs circles around CPUs hands-down) Thks again
I think you made a mistake here at 9:36. "Blocking" means, that the assignments are blocking, i.e. they run sequentially (one waits for the prior to finish). "Non-blocking" means, that the assignments do NOT block, i.e. they run in parallel and are evalutaed immediately.
Is the example of dataflow level correct here? At around 3:40 , isn't it supposed to be: assign out1 = ( (~X&A) | (X&B) ); #newbie here, dont understand why the 1st AND gate is written as (~X&A)&A
Yes, it's wrong in the sense that it doesn't match the logic gate schematics, but it is harmless (A&A = A), and still works the same. The compiler will optimize that out regardless.
Dear Sir Thank you very much for this helpful video Please, I try to write the following Verilog code in Vivado, the synthesis process is OK but when I want to implement it an error signal appear !! module Tog_not (hsync, EOL, q); input hsync, EOL; output reg q; always @ (posedge hsync) begin q
Could be bc you’re driving the same output for two different processes. In VHDL I think this is equivalent to a “multiple drivers” error and I think that means the output can’t be determined correctly. If you think about it at the Logical Level, it may be clearer.
