Quick access revision 1:22 design representation 2:41 Y (wye) diagram 5:08 more on Y diagram contd. 10:04 Behavioral representation 11:02 Behav. repr. example full_adder 12:28 Behav. repr. example (verilog boolean exprsn.) 14:42 Behav. repr. example (verilog truth table) 18:08 Structural representation 19:51 Struc. repr. example (4b ripple carry adder) 21:13 Struc. repr. example (conceptual repr.) 22:04 Struc. repr. example (verilog 4b RC adder) 27:04 Physical representation 27:49 Phy. repr. example (partial description in verilog) 29:10 Digital IC design (a quick look) END OF LECTURE