"You sir are the rare 0.0000000000000000001% of the population" Did you fail math? Or do you know of trillions and trillions of people the rest of us don't?
@@TonyTigerTonyTiger He has simulated reality multiple times and observed that in million million million people thus there will be only 1 person like computer science
00:40 : What is a memory cell and how is made? 3:50 : How are memory cells arranged together? 4:21 : How can you read the content of a cell? 8:25 : Why so much work for just reading a cell? Eheh 9:27 : Summary! I appreciated the video 🤙
This series is beautifully done. I can only imagine the amount of work to create it. One point of correction is at 9:21 refresh interval is stated to be 64 ns, but should be 64 ms.
Great video. I got it right away. Listening to Steve Wozniak talking about when DRAM started appearing and how they chose to go with it because it was cheaper, and how it had to be refreshed all the time, got me interested.
I cannot believe that this channel has that number of subscribers. It worths definitely thousands more than that. Well, thanks for this video i wish that u would be my prof...
An excellent lecture that very clearly explains the structure and principles of a dynamic memory. I wish you will continue to do so for the benefit of humanity and especially for students and engineers who want to know better and understand the principles perfectly.
You are very kind. I am currently working on videos about GPUs and the graphics pipeline, quantum computers and an introduction to programming with VB.NET :)KD
3:05 "When the gate is closed..." that will happen only if voltage is applied to the Gate. But here terms are opposite as in a normal circuit switch. Also thank you for these wonderful tutorials.
Thank you!!! You make my Computer Science book must easier to understand. What I most appreciate about your video is the information is absolutely relevant to what I am reading in this dumb book.
Awesome, I can easily understand the flow of the principle. Thank you for producing the tutotial of this topic. Any Engineer should know the foundation how memory DRAM works when it comes to read and write. Looking forword to finish the rest of the videos in the series.
Excellent video! Clearly explained and illustrated. If possible, I'd only suggest adding a bit of animation. Nothing fancy, just enough to draw the viewer's attention - sometimes it took me a while to actually see what you were talking about.
Great series, sir! Although i have one question... At 6:26 didn't you mean the charge would move from the WORDline onto the capacitor? Since the partially charged wordline is connected to them, not the bitline.
Excellent explanation!!! I've never seen a more didactic video on this matter. I would like to ask you, which book do you recommend me to read, to learn more about the electronic behavior of computer components. I am a Mechanical Engineer with little understanding on these topics but I would like to learn more. Thanks!!!
You're very kind. Thank you. I honestly can't recommend a book because I didn't use one for the DRAM series (but I am sure there some good books out there). I did most of my learning for this online; reading websites and articles, and watching other people's videos. I double, triple and quadruple check anything I learn, dig around to fill the gaps in my understanding, and consult other people on the excellent stackexchange.com I made this series because I wanted to explain to my A level computer science students why it takes the same amount of time to access any element of an array if you know the index number. :)KD
what is the sequential order to watch your videos? I want to learn about computer architecture from starting so have you uploaded other prerequisetes videos?
Using transistors and capacitors from an electronics kit, could I build 2 bit dRAM using this method? And if I felt up for the challenge, would it be possible to scale it up for like 100 bits? I love building electronics and am fascinated with how computers process 1s and 0s
Please can you explain to me how we determine the value of the bit for one particular memory cell, I did not inderstand very well How this Works. Thanks very much.
This is great tutorial. But it is not clear why precharging bitline is necessary. Also not clear is why the voltage on it changes by only a small amount (near 6:10) \delta{V}. Is it because the time duration for which the pass transistor is ON too short? thanks
If I understood you correct, you described the bit line both as reading and writing, i.e. discharging and charging the capacitor. Furthermore this just playing with one of the two bits, the bit 1. And the bit 0 is just there for looks. How that cell is kept out of the way of being detected by means comparing its voltage .... is not discussed at all. Do you mean to say that in order to charge ( write) the capacitor the gate voltage is lowered and once it is charged the voltage of the gate is kept high? And since the capacitor is never fully discharged, for it to be charged the bit line of course has to have higher voltage and for it to discharge the bit line voltage has to be lower. And you haven't mentioned the value of the gate voltage. And for the capacitor to charge or discharge you have to send current to the gate? If so then so many cells are connected in a row all them cell's gates are getting current and the 0 discharged cells will get charged for no reason, i.e. being written to while the other 1 bit cells getting read or discharged. I see some charging ( writing) that has take place in the second row ( the first the the third cell) on the 0 bit cells, while the other two 1 bit cells are showing slight discharge. So I assume that the 0 bit cells in order to be read, some charges are sent there and then immediately has to be discharged somehow.... not sure how that is done. Espcecially if it is ROM memory. It shouldn't be changed.
I think the location of source and drain terminals should be interchanged
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Do the word line and bit line have anything to do with the rows and columns of actual DDR SDRAM? In a x16 device, there are supposed to be 16 cells in a column -- how is this reflected in the topology of the cell array?
Great question! These are actually symmetric devices and don't actually have a drain or source, or you could say the drain and source switch between reading and writing a 1 or a 0.
Thanks for the amazing content! There's one thing I don't get. Why should the cells containing 0 should be recharged? If, after all, they are not charged hence representing 0
Early in the video he mentions that reading the cell is a destructive process and what you point out is why. The bitline and cell will share their charge and move to a new voltage slightly offset from where the bitline was. Once the sense amplifiers fire they will pull the bitline back to where the cell was and this will re-charge (refresh) the cell.
What happened to them cells with no charged capacitors. The 0 bit cells? How do you read those and why have a capacitor there anyway? Unless it is there just in case you want to change its value, changeable. What about the ROM. Are there capacitors there in the 0 value cells and for what unless it is there to change its value too? Maybe it is covered the next video. So far very informative.
This a video about DRAM, as in RAM not ROM. So the cells can potentially be changed from one logical state to the other all the time. So a 1 may be written over to a 0 and vice versa. The 0's are just as important as a 1 as they are both a single bit of information.
I notice that either. According to JEDEC, Memory cell need to be refresh every 64ms. Which mean 16 times refresh operations happen per second for per cell😊
@3:47 "you can see that 'reading' the content of a memory cell is a destructive process". Why? I understand it would be if you were to replace a 0 with a 1 but not why it would be simply reading the memory cell.
To check if a cell contains a 1, it must be allowed to discharge a little. Similarly, to check if a cell contains a 0 (i.e. to check if it has no charge) it must be allowed to charge UP a little. When a cell containing a 0 charges up a little, it effectively 'destroys' the 0 it contained. Imagine a bucket of water: to check if it's full, you have to pour some water out (so it's no longer full); to check if it's empty, you have to pour some water in (so it's no longer empty). At the risk of muddying the water, it may help to bear in mind that there is a minimum amount of charge, below which a cell can no longer be thought of as containing a 1. Conversely, there is a MAXIMUM amount of charge ABOVE which a cell can no longer be thought of as containing a 0.
How the charge is getting transferred for and to the capacitor by applying voltage. i have understood one case that when the capacitor is fully charged and high voltage is applied to gate the charge gets transfer from drain(capacitor) to source (bit line).but how come the reverse is happening means how zero vol capacitor getting partially charged after getting read(means charge is getting transferred from source to drain).could you please explain it sir.
Remember that during the read the bitline is at an in-between voltage. So lower than a charged capacitor but higher than a discharged capacitor. In either case if the transistor is conducting the capacitors move twords that half way voltage.
In case you are like me. Making this in "Circuit Wisard" what Transistor do you need? my reset whit backfire power. So problematic when power open it self, or do other things like open the valve the other way around and other funny problems. No both ways Master Transistor that say: "you shall not pass" when not open. "i can't find the Gandalf Transistor" :-D And my free version P Ch MOSFET work like N or not working.
The layout is very similar but the cells are built from logic gates making them non volatile. Therefore the way it works is somewhat different from DRAM. I will cover SRAM in another video. :)KD
if the all transistor were to be with one capacitor in 100% voltage and other in 0% voltage, then right now is not neccesary to higthering or lessering that capacitors voltage, but on its output sind capacitor get one switch to be output in cero or higt signal... so the reading or writing are synchronicse with output switch and clock to new data or registres, for that the transistor conmuting to Zero or high level if only signal input is in the shiper instant and about gate diode to be negative or positive voltage to ok output being one 1 or 0 digital binary... so our only get free the rampe clock active with the signal binary, in concluscion we only spend the more lessering 1% energía that other system ram, rom or cpu... esto sumado a la refrigeración líquida obtendremos celulares frías o pantallas frías por láser optico... rendimiento al máximo y velocidades muchos mayores de Ram o rom... 👽👽👽
believe me, refreshing every 64 nano seconds is a dream but 64 ms is realistic., please correct your statement., otherwise its a good explaination and that to this refresh rate is temperature dependent, 64 ms under 85 degrees and 32 ms above 85 degrees!
