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ECC vs On-die ECC DDR5 Memory - What Is The Difference? 

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Video Chapters
00:00 - The Start
00:22 - Doesn't ALL DDR5 Have ECC?
01:12 - How does ECC Memory Work?
02:41 - How On Die ECC DDR5 Memory Works
03:41 - What Is The Difference?
04:27 - Is On Die ECC on DDR5 Memory Useless?
05:10 - Protection from 1 or Both?
05:25 - Why Flash Servers Use ECC at the Enterprise Level?
05:45 - The BIG Takeaway
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28 июн 2024

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Комментарии : 18   
@raya4633
@raya4633 Месяц назад
On-die ECC is not a feature it's a requirement because the DDR5 ram chips are subject to a significant rate of error.
@blahorgaslisk7763
@blahorgaslisk7763 Месяц назад
This is correct. But it's not really a problem of the chips being marginal but rather that the memory speed is pressed so high that errors started to become too common to work as intended. The on-die ECC masks the single bit errors that occur when pressing the circuitry to work at these speeds. It's just sorry that we don't get any kind of feed back on the bit error rate.
@blahorgaslisk7763
@blahorgaslisk7763 Месяц назад
Conventional ECC will generate an error message in the system log. That way you can see the ECC errors that are discovered and can decide on changing memory modules before they generates a uncorrectable error. In general you don't see a ECC error in months. A single ECC error is no big thing, shit happens such as stellar radiation flips a bit. One error is just a sign that the ECC works. If you get a several errors from the same DIMM then it's a good chance that a memory chip on that DIMM has deteriorated and it should be replaced before a non recoverable error occurs. This is information you don't get from DDR5 memory stick that only support On-die ECC. Even if a chip on the DIMM has degraded so the on-die ECC has to repair the data more and more often the user don't get any sign of that before the memory really fails. Also standard ECC can detect and repair single bit errors. If two bits of the same 64-bit word is compromised ECC can still detect an error, but it can't repair both bits. That's a unrepairable ECC error and most OS will be set to halt operation if one of those are detected. That's effectively a crash. More advanced ECC implementations has been designed and are able to repair dual bit errors. But the problem is that more parity bits are needed which makes this kind of memory more expensive. Another version in the ECC range can issue a kill bit to disable memory that has generated ECC errors. The idea here is that if a memory chip degrades and starts to throw errors it will be deactivated and less memory will be available for the computer to work with. Yet another ECC implementation used DIMMs without ECC bits, but added extra DIMM that was used for parity bits. I can only remember seeing this used for cache memory on a RAID controller way way back, and I have no memory of seeing it used for system memory. I can't remember the names of all these technologies except I think the technique of disabling suspect memory was called Kill Bit and I think ServerWorks developed that. I've worked a lot with server grade equipment, but a lot of it was ages ago, and unfortunately I've suffered some brain damage since. A lot of memories are fine but my memory of names has suffered a lot.
@andygardiner6526
@andygardiner6526 Месяц назад
I thought ECC was all memory bus oriented correction, not specifically for data on storage i/o channels? Or is that part of the oversimplification?
@MisterPikol
@MisterPikol Месяц назад
can you do a video on ssd's with ecc ram memory ? I recently got an an intel dc s3700 ssd and it is said to have ECC RAM. is that the case for all ssd's with dram ? what are the benefits ?
@MatIndustries
@MatIndustries 23 дня назад
Many thanks for your informative video. One thing is still unclear to me. Does every DDR5 SODIMM have ECC on the die or not? If not, how would i recognize that ?
@InspectorGadget2014
@InspectorGadget2014 Месяц назад
I do believe that the drawing in your right-hand was held upside down, that would be confusing the onlookers, possibly. I do like the approach though!
@InspectorGadget2014
@InspectorGadget2014 Месяц назад
Indeed, up to @02:38, the drawing in your right hand is truly upside down, yet @02:45 it is shown correctly....
@InspectorGadget2014
@InspectorGadget2014 Месяц назад
BTW, I do believe you are not correct @03:33 talking about flash memory with respect to DDR5, it is and always has been SDRAM. (synchronous dynamic random-access memory) Where flash memory has its origins to magnetic bubble memory, SDRAM is in fact small capacitors, with FET's. Flash memory is inherently way slower than SDRAM. (Flash is also serialised memory, whilst SDRAM is parallel accessed) I do not want to be brutal here but you are mixing-up technologies in this topic that might confuse or give incorrect expectations...
@InspectorGadget2014
@InspectorGadget2014 26 дней назад
I dove a wee bit further into on-die ECC for DDR5; In short, on-die ECC only checks the data as stored inside the (SMD) memory-chips. It will do nothing when the data leaves that DDR into another controler-chip, CPU etc. So it will *not* check the data in transit. Regular ECC will check the data between the memory and the destination which/when it is (also) ECC capable. So, why on-die ECC with DDR5? Because the formal JEDEC specification dictates a frefresh-rate of 65msec, but with the often way more denser DDR5 cells (much like QLC flash, compacting more cells into the same space), the chance that a bitflip occurs due to thermal issues, cosmic rays (yes, really!), slower cells somewhere in the package and so forth, is increasingly a worry. So to meet those JEDEC standards for DDR5 and providing a bigger yield during production, on-die ECC can be included into a particular DDR5 memory design. But it is *only* for the data still residing inside that memory. The moment that data leaves the DDR5 memory-stick (to a CPU etc), that on-die ECC has no meaning at all. Full stop. So, in case you need ECC with your DDR5 memory-stick, you will need a DDR5 ECC memory-stick... That on-die ECC for DDR5 is just clever marketing from the memory-manufacturers.
@BobHannent
@BobHannent Месяц назад
I'm really not sure this explanation is as easy to understand as you want it to be.
@junior-OG
@junior-OG Месяц назад
😂
@BoraHorzaGobuchul
@BoraHorzaGobuchul Месяц назад
If that's not easy then perhaps you should outsource your basic IT tasks
@robertlee6338
@robertlee6338 Месяц назад
On-die ECC is a mechanism that allows OEM to sell ram that is FAILING silicon.
@reabstraction
@reabstraction Месяц назад
Yeah no It's due to mandatory by spec
@robertlee6338
@robertlee6338 Месяц назад
@@reabstraction The spec was amended to include On-Die ECC because without n die error correction failure rate was running 34%
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