FPGA #19 - A look at the iCE40 Technology Library

Подписаться 15 тыс.

Просмотров 1,1 тыс.

50% 1

Related Github repo:
github.com/joh...
Verilog and other topics in this video are being discussed in the Nouveau project in this discord: / discord
You can support this channel on Patreon! / johnsbasement
This video is part of a RU-vid Playlist: • FPGA
Music used in this video (Vibe Tracks, Alternate) was downloaded from the RU-vid Audio Library: www.youtube.co...
#verilog
#fpga
#ice40

Опубликовано:

15 окт 2024

Ссылка:

Скачать:

Готовим ссылку...

Добавить в:

Мой плейлист

Посмотреть позже

Комментарии : 9

@DennoWiggle 5 месяцев назад

That is interesting about the SB_WARMBOOT technology block. I always learn something new in your video's. Thank you.

@JohnsBasement 5 месяцев назад

I thought it was cool when I first read about it too. I am looking forward to playing with it!

@ChrisJackson-js8rd 5 месяцев назад

looking forward to more detail on PLL :) it seems like almost all modern fpga's support some degree of live reconfiguration. but I haven't quite got my head around how that works mostly it seems to be used to reroute i/o, like in a dsp that might split bandwidth among different channels

@JohnsBasement 5 месяцев назад

The PLLs are pretty cool. The ICE40HX warm boot looks like it is a full reload & reboot. Fancier modern chips allow for partial-reconfigs where you can keep part of your design running while some other portion of the FPGA is reloaded!

@paulwratt 12 дней назад

Hah .. rabbit hole :)

@HylaTube 5 месяцев назад

Figure 5.1: D_IN_0,1 and D_OUT_0,1: those are not switched, are they? Would make much more sense to me …

@JohnsBasement 5 месяцев назад

The IN and OUTs are switched or the 0 & 1 are switched? I think it all looks OK to me. The 0 are on the rising edge and the 1 are on the falling. Right?

@HylaTube 5 месяцев назад

What I meant was, the D_INs look like outputs to me and vice versa. No? Amateur here … ;) Christoph

@JohnsBasement 5 месяцев назад

@@HylaTube They appear to be named from the perspective f the FPGA as a whole. So the D_IN is an output from the pin input buffer. 🙂