Gigabit Ethernet + FPGA/SoC Bring-Up (Zynq Part 4) - Phil's Lab #99

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Gigabit Ethernet PHY (physical layer) and AMD/Xilinx Zynq SoC (System-on-Chip) configuration. Schematic and PCB layout/routing overview, RGMII/MDIO/MDI signals, Vivado and Vitis configuration, fixing driver bugs, example TCP bandwidth performance application, and test.
PCBs by PCBWay www.pcbway.com
[SUPPORT]
Free trial of Altium Designer: www.altium.com/yt/philslab
Patreon: / phils94
Mixed-signal hardware design course: phils-lab-shop.fedevel.education
Advanced Hardware Design Course Survey:
forms.gle/X4jwvtZeJ1jTXh7r9
[GIT]
github.com/pms67
[LINKS]
Instagram: / philslabyt
iPerf: iperf.fr/iperf-download.php
PHY datasheet: datasheet.lcsc.com/lcsc/19121...
[TIMESTAMPS]
00:00 Introduction & Previous Videos
01:05 PCBWay
01:45 Altium Designer Free Trial
02:11 Hardware Overview
03:36 Schematic
05:35 PCB Layout & Routing
06:37 Physical Layer (PHY)
07:14 Vivado Ethernet Set-Up
11:10 Vitis TCP Performance Server Example
12:03 Driver Fix #1 - Autonegotiation Off
13:02 Driver Fix #2 - Link Up/Down Bug
16:26 Hardware Connection
16:42 COM Port Set-Up & Programming
18:14 iPerf Tool
18:37 Bandwidth Performance Test
21:09 Summary
22:08 Outro

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Опубликовано:

5 авг 2024

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Комментарии : 63

@scrubbypiss 9 месяцев назад

I wish this series was out back when I was doing an internship to design a custom Zynq dev board in 2021. It is incredibly well explained and shows a very well balanced, step-by-step workflow to design and test a Zynq board. Compared to reading incredibly long datasheets and getting lost in all the Xilinx UGs, this is a godsend.

@teddyjamilonatefreire8797 Год назад

What a nice job! Congrats Phil. I really love your videos

@PhilsLab Год назад

Thank you very much, Teddy!

@asad2880 Месяц назад

Love this video. Absolutely to the point yet comprehensive.

@grpdv 4 месяца назад

Hats off to you! It must be expensive/time consuming to produce the video of such impressive quality.

@Dinkleberg96 Год назад

What an AMAZING job, as always!

@PhilsLab Год назад

Thank you!

@fireracerworkshop8251 Год назад

Really awesome to see that you're also using add blocker 🤣 Really love your videos sir.

@dnyaneshwarshingare1403 Год назад

Such great work thank you Phil 🥰🥰

@PhilsLab Год назад

Thank you :)

@saravanakannan6686 Год назад

Phill Thanks for this video

@PhilsLab Год назад

Thanks for watching!

@seiftamazerti4547 Год назад

Great job 👌..like always

@PhilsLab Год назад

Thanks, Seif!

@AdoobII25 Год назад

Love you Phill

@PhilsLab Год назад

Thanks, Mohammed

@yellowcrescent Год назад

Nice! Impressed that the Zync can handle the nearly 1Gbps throughput to/from the PHY, and the suite of test programs that Xilinx has provided is pretty nice. Seems like they embedded iperf in a standalone program. At least in Linux, the Realtek PHY "quirks" will have already been worked-around in the driver :D

@PhilsLab Год назад

Thanks, Jacob! Yes, pretty impressive chip the Zynq is.

@AdoobII25 Год назад

Keep in mind that while the throughput is 1Gbps, the clock speed at which the FPGA interface to the PHY (RGMII) runs at 125MHz. The Zynq should be able to handle faster clock speeds at its IO :)

@tpa2640 4 месяца назад

it would be REALLY interesting to see how to design a board with a 10GB ETH interface. (and to give more challenge, using the new IX Industrial connector !)

@gryzman Год назад

good stuff, so to speak ;)

@PhilsLab Год назад

Thanks, Gregg!

@berberger4814 Год назад

not gonna lie, I have the impression that you are really good, but I am still impressed that it makes 900mbit/s+ (probably it wasnt that hard for you, but still)

@PhilsLab Год назад

Thanks! I'm glad it worked out first try on this board as well, but I was more worried about the DDR interface, as there's far more that could go wrong there.

@parshvapatel8484 Год назад

@@PhilsLab I have seen that it is possible to install linux on old phones but is it possible to add something like ft232h or raspberry pi pico to make that smartphone a partial raspberry pi .

@T0pbuzz 8 месяцев назад

Great video. For ENET0 in PS block, why did you choose HSTL 1.8V and not LVCMOS 1.8V? Does the Marvell PHY datasheet say to use HSTL?

@Jonathan-ru9zl Год назад

Hello, How you figured out this 12:51 change in bsp? What other important options this wizard [bsp settings] provide?

@user-ex1uv4su2b 8 месяцев назад

Thanks for your information. It is great. Could you please tell me if we are able to flash QSPI through Ethernet? not through Jtag. I am new to FPGAs. Thanks

@alexisgalindoflores4089 11 месяцев назад

Thanks for your work, very useful. I would like to ask you if you know some method for updating the SW of zynq using the ethernet connection. For example, through an embedded web server. It would be very interesting. Thanks a lot.

@Jonathan-ru9zl Год назад

Genius

@PhilsLab Год назад

Thanks, Jonathan!

@rushikeshpalkar8884 Год назад

Hey, can we get to know when the new course be available?

@ArieLash01 Год назад

Thaks Phil I found a change to make on my pcb I am doing almost the same design but Kicad Not altium I just copied your Rj45 I put a JXD0-0001NL the HR911130A is a lot Cheaper ? Why did you not use the Maxim chip MAX20029 it seems a better psu. You are a lot faster than I am I started in December and am only now at a clean SCH with no errors. I am thinking using 4 chips PAM2310BECADJR so-8 I am going with Hirose Connector . You have saved me many Hours as you have shown the Bringup I am at least a few months away from Bringup . I do my own BGA soldering I am doing it all in house at home. not PCBWAY for assembly .Arieway

@tornadoflore Год назад

Another highly educational video. Thank you Phil. The example programs are based on some kind of RTOS ?

@michaelcummings7246 Год назад

No OS so far just running directly on the hardware for this simple testing stuff.

@PhilsLab Год назад

Thank you! No RTOS used for these examples I believe.

@ALTracer Год назад

These lwIP examples are simply lwIP stack in standalone NOOS mode (so no RTOS) and a few applications from its app collection. Neat if you don't want to deal with full Linux bring-up yet. I'm more surprised that they didn't combine both iPerf2 TCP & UDP servers with ICMP echo and TCP echo server. I did (most of) that when tinkering with STM32F072B-DISCO and USB FSDEV RNDIS -- it managed 6 Mbps throughput over USB 12Mbps while fitting in ~96/128k of Flash, 16k of SRAM and serving a webpage at the same time!

@di987654321 4 месяца назад

Hi Phil do you have the schematic published? please let me know thanks for your video

@buddhabenarji2844 Год назад

Hi Phil, thanks for such a great video. I'm trying to send 2 HD-SDI video feeds and one UDP communication protocol on a single ethernet connection. Could you please help me on how to achieve that?

@biker2109 Год назад

have you looked at NDI from Newtek?

@haakonness Год назад

HD-SDI has 1.5Gbit/s or 3GBit/s datarate unless you compress it. So you would need to either compress, or use a 10Gbit/s PHY. If you need to ask, I am unsure if this is something you should try to do with FPGAs. It would be easier doing with ready made hardware, like SDI input cards, a computer, and open source software for encoding/sending over ethernet. NDI is a simple solution yes.

@asmi06 Год назад

Just a heads-up - whenever you regenerate bsp (for example after changing settings or refreshing the bistream) all of your changes are going to be *gone*! Ask me how do I know this ;)

@robby091000 Год назад

I'm doing a project where I'm sending data through AXI into the PL and using the PS to send that data through Ethernet, i have most of the AXI work done and data is arriving in memory ready to be send through Ethernet but here i hit a roadblock and that I'm not familiar with the lwIP library and exactly how data transfers work with the PCB structure and accept calls, is there any documentation or examples you know you can refer me apart from the lwIP documentations and reverse engineering the xillings examples? I have done this already but i still have a hard time understanding the subject. On a side note i appreciate all your videos, you are the first person i go to when i need to learn something new on PCB design and my first go to person when i recommend sources on how to do it.

@PhilsLab Год назад

Thanks, Robby! I'm afraid other than the docs/app notes and examples, there isn't too much info on this online from what I have seen. I hope you can find a solution though!

@minhkhoa445 5 месяцев назад

Hi Phil, I am currently trying to bring up Gigabit Ethernet on a Zynq board using Broadcom B50612D PHY. Currently, the PHY clock is supplied by a 25MHz crystal. In PS IP core clock configuration for ENET0, I see 4 options: ARM PLL, IO PLL, DRR PLL, External. Which option should I choose for my board and is there any differences between each option?

@vinaychandratre4188 4 месяца назад

Where can we buy the populated tested board ?

@novavela 5 месяцев назад

I could not get higher transfer speed than 59.7 Mbits/sec on several reference boards (microZed, XU8, ...). turns out to get top speed, I needed to increase LWIP bsp settings tcp_wnd from 2048 to 40000. Now I get 943 Mbits/sec on all these boards.

@Quantum_Dots Год назад

Is it possible make a board like Raspberry Pi 4 with functionality of FPGA ?

@Jonathan-ru9zl 2 месяца назад

Hi. How did you install iperf2.0.9? Did you use Cygwin?

@chaochang1305 Год назад

the debug porcess is great,if you don't tell me the method,I might never know whot the problem is.

@BHSAHFAD Год назад

what is your "home rooter"? i always thought it was called a "router"

@ZayMeisters Год назад

What was harder, the DDR memory or the gigabit ethernet? I feel like it would be DDR, but this looks difficult as well. Anyways, another great video!!!

@PhilsLab Год назад

Thanks! DDR set-up was surprisingly simple and running in only a couple of minutes (thankfully). The Gig Ethernet would've been okay as well, hadn't it been for those few "bugs" I had to fix in the driver.

@AlbertRei3424 11 месяцев назад

@@PhilsLab I think he talks about the hardware design, and of course, DDR routing is way harder that Ethernet !!

@user-xx3zj3xb9b Год назад

Not gonna lie, vitis/petalinux has a lot of weird driver code bugs.

@prashkd7684 Год назад

May i ask what're your plans for this board ? Are you planning to sell it as dev board at all ? This half FPGA half micro board is quite interesting.

@hidde3064 Год назад

Listen closely at 0:36

@PhilsLab Год назад

This is part of the upcoming 'advanced hardware design' course. When I release that, I'll also be releasing the board for sale!

@phrenologisto Год назад

Are we talking about an application agnostic dev board, here? What are the edges of this system's capabilities? Seems like a foundation for a tricorder like device, especially with AI becoming a more an more functional author of code, is this a piece of hardware where a person could ask AI to solve a problem and it could use this as its connection to the outside world, appropriate sensors attached, of course. Very cool! FPGA programming and utility are a bit beyond me at the moment but im following along like a baby swatting at a mobile. What is the best application use case to take advantage of all components of this system? What were you imagining when you designed this?