Outside the scope of this video but FWIW, a trick I learned from an RF engineer to mitigate the effects of plane gap crossing is to provide a "reactive short" through the use of bypass capacitors nearby the signal crossing. For example, a high speed signal referenced to a 5V plane jumps a gap to a 3.3V plane, you can potentially mitigate (not eliminate) plane crossing effects with a small (0402) ceramic capacitor connected between 5V and 3.3V placed near where the trace crosses the gap. I personally view this as a hack and your mileage will vary, especially at frequencies above 10 GHz. As always, simulation is key.
Since capacitors have self-resonance the hack is limited in effectiveness only up to the ~100 MHz range, so that's basically where it limits the bandwidth. That's fine for single-ended stuff like SPI as long as its rise time is not too fast, so that addresses most components with SPI interfaces. I wouldn't dare do it on DDR. And with a fast differential interface, the other trace provides a reference anyways, but effectiveness also varies depending on stackup, materials, spacing between traces in the pair, etc.
Hi Zach, thanks for diving into this topic! I'm relatively new to the RF world, and I was reading that a higher "return loss" is actually desirable, however the simulation you show seems to indicate the opposite. At about the 9:15 mark, you said that the simulation results for the split reference planes have a "pretty high return loss compared to" the continuous plane reference. I understand return loss as "the loss in the return signal". If the return signal is the reflection (which we don't want), then the return signal loss would be infinite, or in other words, the load would consume all of the power. Could you explain a little more about the s-parameter simulation result that is shown in this video? Why are the units in negative dB, and could you help me understand what I might be missing? Thanks!
If you are referring to a stackup such as SIG/GND/PWR/SIG and the PWR plane is split into different rails, the answer is no you are at risk of radiated emissions and impedance discontinuities unless the split regions are very small. One way to try and get around this is to use copper pour on L4 in order to provide nearby ground reference but it is no guarantee to work. It is better to only put slower signals or configuration signals on L4 in this stackup and keep the faster signals (such as SPI or higher data rate) on L1.
Is this always assuming the gap is between fingers of the same power pour? How badly would things change if, for example, one plane was 5V and the other side of the gap were only 3V?
Just based on an impedance calculation in that gap, the value of the plane voltage should not matter. I was not really assuming there was routing over fingers in a single power pour versus routing over two different pours. At least with routing over a finger, the return path will still exist somewhere in that pour so I would think you get less radiation compared to the case of two totally different pours. But still, with two totally different pours, the voltage differences should not matter.
I meant move the pads in the simulation model into an inner layer. If it is an SMD pad you can set it into an inner layer. Then when you export the design to an ODB++ archive, the simulation tool will allow you to set your port into the inner layer without modifying the extracted linear network. This removes the influence of vias on the input to the transmission line.
Hi Zach, you said that one trace can act as a referance for another trace. But is it really work like that? According to rick hartly each trace act like a single ended the differnce is that they coupled more or less to each other to determain thier diff. Impedance. Another advantage is that they can ignore offset diviation. Also, does the return current always goes through the referance plane above or down because of the feilds between the planes?
Yes it does really work like that if you look at how a differential receiver works. The receiver is measuring the potential difference between two traces. By definition, this means one trace is the reference for the other trace at all times. There is always an interaction between the two traces that is mediated by the spatial distribution of the electromagnetic field around each trace. When the ground is near the traces, this changes the electromagnetic field distribution around the traces but it does not change the fact that you are measuring a potential difference between the two traces. When a reference plane is present, it will contain some return current because that is physically required for the electromagnetic boundary conditions in the system to be satisfied, it does exists due to the fields near the planes.
Thank you for your answer. Still im not sure i get it. The receiver isn't measuring the potential of each trace with respect to his ground? Also if the lines are not perfectly balance there will be much more current flow through ground.
@@naorp2025 Yes that is what is being measured, but it is equivalent to measuring the voltage between the lines. The differential voltage is (VPos - VGND) - (VNeg - VGND) = VPos - VNeg = 2Vpos. This works because the receiver uses the same ground reference for both traces. If there were an imbalance then there would be some current flow through ground that would not be symmetric about the midpoint between the two traces.
ZACK CAN YOU PLEASE EXPLAIN ABOUT EYE DIAGRAM SIMULATION LIKE WHAT IT IS(INCLUDE ANY SOFTWARE REQUIRED)? WHERE TO USE? AND HOW TO SIMULATE? MORE USEFUL IT IS.
