CMOS inverter - charging & discharging time Clock skew - adv & disadv Types of power dissipation in CMOS inverter Latch & flipflop where we use & o/p waveform Aspect Ratio of MOSFET changes parameters of MOSFET how? Order of priority of timing,power,area while designing IC 3-types of inverters and comparing their performance Recents for Static & dynamic power dissipation and dependency on Threshold voltage Power dissipation reduction? Which parameters to vary to cover power dissipation for above Vlsi design flow Setup & hold time ( why,how,for latch too) Latch using mux Puzzles Resume
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Hi, Digital Integrated Circuits by Jan M Rabaey is a standard textbook on the subject. you can refer the section "Timing Properties of Multiplexer-based Master-Slave Registers" in Chapter 7 - DESIGNING SEQUENTIAL LOGIC CIRCUITS, of Rabaey (page no. 308), to see why setup and hold time exist. You could extend similar reasoning for other circuits.
