Analog Devices Basic Interview Question

Подписаться 3,6 тыс.

Просмотров 14 тыс.

50% 1

Hello Guys,
Small apology for the big delay but finally we are here with a new very interesting question on Inverter circuit.
Let us know if you guys have some doubt and try to answer the type of feedback and why?
One of my friend appeared in the interview for Analog Devices he shared the question to us. Feel free to share the question on "saurabhtri333@gmail.com".
Thank You :)

Опубликовано:

30 апр 2023

Ссылка:

Скачать:

Готовим ссылку...

Добавить в:

Мой плейлист

Посмотреть позже

Комментарии : 28

@amitbar7266 Год назад

A CMOS inverter with resistive feedback where transistors are self-biased in strong inversion is designed and optimized for low NF and high IIP3 in LNA

@bangaloriansvlog 5 месяцев назад

The same question was asked to me during my internship interview at Synopsys.

@mirzaamaan6937 Год назад

Please bring more such videos these are super useful

@aayushADE334 Год назад

what i can think is that since no current flows inside the mosfet so output is shorted to input and both the mos comes in sat as vds= vgs which results in vout = vdd/2 as per inverter characterstics .

@KK-bj3mq Год назад

Very interesting, Waiting for next session

@anushatadamari3185 6 месяцев назад

Please do come up with more videos..

@StandforAjdetray 4 месяца назад

Much appreciated sir Very interesting and waiting next session

@AnalogABC Год назад

bro videos are really good pls dont stop making videos

@saurabhtrivedi6181 Год назад

Thanks man :)

@landrover8135 Месяц назад

When i try to solve the small signal gain around the switching threshold, i get the small siganl gain is {-(gmn+gmp)*{1-[1/(R*(gmn+gmp))]}}/(G+gmn+gmp)...If (gmn+gmp)*R < 1 , then this acts as a buffer otherwise as inverter...is my analysis correct ?

@IcRDlayout 5 месяцев назад

Thanks 😊

@kaustavguharoy4532 Год назад

for each of the two modes the time constant of the circuit remains same , Is it?

@analogeasy-peasy7559 Год назад

So as discussed in the video make an R and C model of the circuit. If the R charging and discharging is same then Yes. Clearly here the circuit gets changes so it should not be the case.

@AnalogABC Год назад

positive feed back ? , and ig here application of circuits might be other than inverter ig gain ? idk

@analogeasy-peasy7559 Год назад

it's actually a feed forward feedback

@user-pm2rz7tv3o 11 месяцев назад

there is no gate current.what about that

@amitjana8172 Год назад

Here if R tends to infinite then there will be no feedback, if R has some finite value then the circuit will acts as a negative feedback circuit. If we set the input to 0 and break the loop and increase the voltage by some +ve amount then NMOS will be on and PMOS will be off. So as it is a CS amplifier ckt then there will be 180 degree phase shift in the op, so for increase in input output decrease , so it is a negative feedback ckt, for finite value of R. Am i right bhaiya?

@amitjana8172 Год назад

Bhaiya could you please make a video of buffer related questions, like calculation of 3 dB frequency, or kindly refer any resources from where I can practice this kind of problems.

@amitbar7266 Год назад

Yes, - ve feedback,,and actually finite value of R will modify the overall Gm and overall Rout of the amplifier...

@analogeasy-peasy7559 Год назад

your analysis is right actually but just think about this- the feedback is the one which effects the input ( alter it change it) but in this case it is not possible since we have a forced input. This kind of feedback os called feed forward feedback.

@amitjana8172 Год назад

Thanks bhaiya

@maylok77 Год назад

please answer me why they add capacitor at the out?

@analogeasy-peasy7559 Год назад

Adding the capacitor makes the output voltage stable. The more the capacitor the more stable will be the voltage. In real designs as well we put dynamic capacitors inorder that our circuit just not start reacting to small noises and all. Would suggest you to see RC Network questions discussed here in the channel.

@IcRDlayout 5 месяцев назад

CL is placed to the Vo 😊

@ntdglobal2510 Год назад

I have some questions. What is the effect of rise/false time of input on transient response? When can CGD be ignored? The resistor will be a feedforward path, not a feedback path if the voltage source is ideal.

@saurabhtrivedi6181 Год назад

Hii, so if your input is having a higher rise time or fall time then depending on the values of load capacitor, R and Ron( p or n) the output will get time to settle down to its final value ( which could be deduced by the formula mentioned in the video ). If the time constant is lower it will follow the input else will slow it down. If you have steep input with lower rise and fall time then also again depending on the loading it will follow or slow down the input. Now this question gets better if we have clock as an input to it then if the loading is higher and the input steep in nature than probably this will result in lower voltage swings at the output. Yep, you are right that this can’t be stated as a feedback until we have a forced supply at its input. Kudos on that🎉.

@mrx1167 Год назад

Can yu give little brief how do yu define it's not feedback, feedforward.

@saurabhtrivedi6181 7 месяцев назад

@@mrx1167 feedback is given directly to the input but since input is an ideal source so it won't be possible for it to be changed but this feedback is also connected to the output which is not tied to any ideal source hence known as feedforward not feedback ^_^