but sir isn't the combinational circuit used in 4 bit register is actually a 2x1 mux??? it will be easy for all to understand the load operation through mux circuit instead of combinational circuit.
Here I was referring to the propagation delay in the clock signal. when you apply the clock through the AND gate then clock signal to the register will get delayed.(Its called clock skew, I will cover that in the very next video). And it can cause synchronization issue in the large digital circuits. So, here instead of doing that, the clock signal is applied directly. And the combinational logic is implemented in the data path. Of course, these additional AND and OR gates will increase the propagation delay in the data path. (Flip-flop will receive the input after finite propagation delay). But as far as the inputs satisfy the setup and hold time condition of the flip-flop, it will not make much difference.
That is how the results are stored. When the load is low, then Q will be connected to the D input of the flip-flop and the flip-flop will retain the same state. Please check at 6:17.
In the subsequent videos of the register, I have already explained it. Please check the recent video. In that, D flip flops have been used. But you can use jk flip flop also. Just use JK flip flop as D flip flops. Basically you just need to apply the input to J input of the flip flop as it is, while the same input should be applied to K input of the flip flop via NOT gate. In the flip flop conversion video, I have covered that. Please check this video for more info: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-bl77FRTAXWA.html
You need to stop with that weird intonation at the end of sentences. Try just speaking the whole sentence in the same intonation as you do on the start :)
