Investigating a Nixie Clock Failure 

Great! If it was on me, I would share just this type of information as this is my daily work. Just dont want to scare off people with talking too much about problems :-)

@@daliborfarny this shows a level of commitment and love for your craft that gives confidence the the owners, they know they can turn to you if there is ever a problem and they will be heard. I am blessed to have discovered your channel and can't wait to purchase my own.

Thank you, this is always very nice to hear. I will be happy to assist on email dalibor at farny.cz

​@@daliborfarny, the attention to detail is absolutely amazing and, quite frankly, thankless. The amount of knowledge and research and development which goes into designing, producing, selling and putting a damn warranty on something like this is staggering. The amount of troubleshooting skills you have on various electrical, PCB, production, design, etc is quite amazing. I will definitely be buying one. Look for my order in the next couple of weeks. Ray Chammas Columbus, OH USA

@@RaymondRChammas Well said, I could not agree more!

I’m saving up to buy one !

Hi John, thank you for nice comment. You are right, the photo/video cant catch beauty of the nixie tube ;-)

Thank you very much for this comment, lots of valuable information! Just few quick explanations - we didnt have problems with EMI, this was fine with the previous designs. It is only better with new design.. We use increased clearance (2mm) on HV lines - exactly for the reasons you mentioned. Thanks for the tips regarding the layers and EMI - we will sit on it and discuss what we can do better for next revision. Keep in touch :-) PS: Je na Vás nějaký kontakt? :-)

@@daliborfarny V youtube profilu mám doplněn pracovní mail.

Personally i would like to separate DPS for electronic and nixie tube mounting and connect them together by ribbon cable( or direct connector)... this would solve "all eggs in one basket" problem and mechanical issues too since DPS for nixie tubes can be single side with nice thick tracks mounted from inside by 4 screws per nixie tube...

heat cycle - very interesting method, thank you for sharing it! the white shop was quite good idea, more coming soon..

Hi Zachary, your kind comment was the first message I read in the morning, it made my day better - thank you for it! Thank you for being our customer!

Hi, thanks for the information! We now use mainly Gatema.cz and Printed.cz, both very reliable. We increased via drilling and traces spacing and since then we havent had a single issue with any of the boards.

Hey, we dont make custom tubes - this was first one made to order. All our tubes are exhangable - from the pinout to the size/shape.

Same.

Traces thickness recommendation has zero merit past current handling capacity and impedance control - absolutely any fab can nowdays handle 6/6mil rules for 35um finished plating. The norm is optical inspection of all layers before lamination and 100% coverage e-test of finished panels. Via filling is intended for absolutely different purposes and does not help with the problem presented in video at all (actually can even worsen it, especially if overplated). From solely the PCB reliability standpoind of view, its not even optimal to do soldermask tenting of the vias. Current handling capacity of even smallest technology permissible via in comodity technology is way way higher than the order of magnitude of 10mA - the stitching becomes important one or two magnitudes above that - depending on via drill diameter, which can drastically infulence its current handling capacity. Heatsinking by surrounding copper (be it power trace or better yet polygon) plays important role as well. Impedance of the via usually matters way more in most cases, and in some less common the ohmic loss (Vcore rail for MPU or FPGA) - but that is outside of the scope of the design presented here. Recommendation of putting the HV lines on outer layers as optimal is wrong. Whenever possible, they should be routed on interal layers as the surrounding laminate has much better insultation properties than what is possible to obtain on outer layer. Soldermask is just that - it is NOT an functional insulation layer and minor voiding defects are allowed and normal. Surface resistivity of any insulation material will be always worse than in its bulk, even in pristine conditions (which won't be maintained over time). Post-manufacturing cleaning is hard (and there is no such thing as no-clean flux!) Also depending on the edge rate (if some of the singals are switched or AC), EMI will get much worse. The recommendation does not hold true for high edge rate signals at all either - there you actually care most about low impedance return path beneath provided without any voiding, and layer placement/stackup is more governed by impedance control of those signals and mutual crosstalk, not crosstalk as agressor to other slow nets around. Suggestion of keeping both groundplane and power plane (single rail) totally void-free is bit off as well - it is absolutely normal to have mixed signal polygons and even some routing on power planes, the ground is what usually is the important reference plane that is good to aim to keep void free - even there, exceptions do apply. Note that by that I am not implying that the power rail does not serve absolutely same purposes from RF perspective (reference), carefull planning of the adjecent layer routing has to be done, should you decide to do mixed net pour there. BTW: the PCB mfg is local, reputable and with good quality control. They have had almost flawless track record with all the companies I worked with and for past some minor cosmetic defects in single case which got promptly admitted and respinned at zero cost. It is very good idea to have a good long ponder about the causes before trying to play shift the blame games.

​@@Konecny_M Trace thickness does affect things. If you can add thicker traces, you absolutely should (for slow signals at least). For example when you do panelization you have uneven etching and in some cases the PCB factory will remove these PCBs or mark them for you. It is one of the reasons many PCB factories make more PCBs than you order. PCBs fail in different stages at the PCB fab and one reason is over-etching/under-etching. (I've seen 10mil traces being reduced to nothing on the edges of panels, accidentally scratched, etc). Just my opinion, use your own judgement. But with a PCB this big it wont hurt making them thicker. Via filling, I meant with solder sorry. Obviously any other filling wouldn't work (I would still go with larger Via holes and tenting). Vias yes can handle alot of current (which unfortunately varies with factories, and day of year), but I tend to over spec my designs when I can. Its easier to say, enlarge vias or add more, than sitting down and explaining that even though your WiFi module consumes 200mA average, you should spec everything to 2 Amps to account for spikes, in-rush current, voltage drops, etc. Its a RU-vid comment after all. I agree that HV lines can be positioned more optimally, my original comment was meant to be short. Not dumping a giant textbook response, as its hard to explain some of the reasoning. For example, HV traces ideally shouldn't be on the top where the majority of the other signals are. But also the bottom side is exposed to the customer & will radiate outwards. But if you need to put them in the middle layers you need to have a lot of experience with ground loops, not cutting the internal planes, etc. unless you know what you are doing. Regarding HV switching lines (or high current) being near other signal traces, things will couple one way or another so if you can put a ground line between them, distance them or put them away on a different level then better.. The power plane can be segmented yes, with ground more care needs to be taken. Soldermask seemed a little weak on my opinion, maybe not as scratch resistant as others. Especially matte black which is usually the weakest of all. Also the via thing, well its still a via failure so I don't understand why I am not allowed to comment that I am skeptical about it?

@@marios2liquid I still disagree with the tace widths. You are at freedom to fully utilize the design rules class you used for the design and paid for - unless you step down the whole design technology class, you won't get benefited in any way by the manufacturer price-wise. Rejects are totally expected (and you already paid for them amortized in the cost per given design rules class). They really should not happen due to under-etch trough, that is a very bad sign about lack of process quality control of given fab.

Integrating sockets into pcb is easier, there are no sockets for our tubes available - we would have to develop them. Such solution would be also bulk, not fitting into thin clock..