Hello everyone. I hope you are enjoying the lectures. You can find the latest lectures on Computer Architecture (from 2017 to Present) in our new RU-vid channel: ru-vid.com
Big thank you for making these publicly available. I do study in an unrelated field but I have a background in EE. I still find EE and CS very interesting and I want to understand more than just the fundamentals, so I hope I will enjoy the course :)
Thank you very much for making this available to everyone. I am truly enjoying the lectures and assignments. I intend to slowly go through as many the lectures as possible and document any findings, research results and answers to exercises which I will be glad to share with you if you are willing. Thank you for the excellent work that you do to advance technology for the future.
WHY WOULD ANYONE EVEN THINK OF DISLIKING THESE? WE ARE GETTING LECTURES ON FOUNDATIONAL TOPICS THAT WILL HELP US GET GOOD JOBS, LITERALLY FOR FREE WHILE THE STUDENTS THERE PROBABLY HAD TO PAY THOUSANDS AND THOUSANDS OF DOLLARS FOR THIS. GOD BLESS ONLINE EDUCATION AND RU-vid AND OF COURSE, THE PROFESSORS AND THE CONTENT CREATORS.
Soon that job will be outsourced or you’ll be fired when the project is over. Automation will take away these jobs first. You are not passionate about it why do it? become a lawyer or doctor for money not this.
@@cardcode8345 1) I am passionate about these and that's why I'm learning these outside of school. 2) As someone who is in academia, I can tell you that the only way to stay on top of automation is to know enough so that you can create these automations yourselves. Automating lower level tasks is how CS moves forward. But it takes another CS student to actually create these automations.
Information costs next to nothing to duplicate. To *not* have quick free access to valuable information which was already recorded should be a moral outrage. University shareholders and boardmembers are all parasite scum.
I don't know if this comment will be seen by anyone. If you are reading this, don't get intimidated by the professor or the student answering all the questions continue watching the lecture series and things will get more clear per video. You can also use Patterson & Hennessey book if you get stuck with something.
hes my teacher, check out "onur mutlu lectures" here on yt for a whole 2nd semester course for computer achritecture.. there might even be a master course on there..
Studying at MIPT. Had this course (on Russian, of course) for all the spring semester. Turns out there were some little details that I missed on my lectures but yours included it. Thank you so much for uploading these lectures online
Thank you is all I can say. Democratising the acquisition of knowledge and high quality teaching is one of the truly extraordinary things about the internet age. Higher Education institutions who do so, for me, instantly gain my respect and good grace.
Türkiye'de bilgisayar mühendisliği öğrencisi olarak sizi geç keşfetmenin üzüntüsü ve sevinci içerisindeyim. İlgimi çeken alanda sizin gibi birisini görünce motivasyonum ve çalışma isteğim arttı. Umarım bir gün sizinle tanışma ve çalışma fırsatı elde edebilirim. Saygılar.
Thank you so much for making this available! I studied physics here in the Netherlands and have always wanted to learn more about this subject and only figured this out after passing my MSc degree. Now we can enjoy this lecture series about this amazing subject at our own leisure, thank you!
I am very glad to find the new update of year 2015. A few days ago , i just started to watch the 2013 of the same class of Prof Onur Mutlu . Compare to the old , you will find the classroom is new ,the equipment are new , and the Prof. is handsome still. LoL :)
Fantastic video and lecture style! I'm working on a RV32IM soft processor but I haven't taken my schools computer architecture course yet (just comp org), so there's a lot to learn. I look forward to the rest of the series!
I love learning and teaching in this field and I saw many courses of Computer Architecture,this is one of the best and I hope someday we see this course in Coursera ,thank you so much Prof.Mutluu
A key factor in determining the cost of an integrated circuit is volume. Which of the following are reasons why a chip made in high volume should cost less? 1. With high volumes, the manufacturing process can be tuned to a particular design, increasing the yield. 2. It is less work to design a high-volume part than a low-volume part. 3. Te masks used to make the chip are expensive, so the cost per chip is lower for higher volumes. 4. Engineering development costs are high and largely independent of volume; thus, the development cost per die is lower with high-volume parts. 5. High-volume parts usually have smaller die sizes than low-volume parts and therefore have higher yield per wafer
Great explanation, Prof. i'm through 54m into this video, i think using separate row-buffers for each core would solve this issue. Like we do with servers, having multiple cache servers, replica of main servers for data access. Like wise, instead of mutli-cores with one DRAM and single row-buffer, keep the multi-cores with one DRAM but same number of row-buffers as cores. The OS scheduler will do the rest.
Unfortunately there aren't many jobs in the field of hardware engineering even in countries like USA China and Japan that actually produce the world's hardware. Web development, networking and AI have way more jobs so less ppl take this course in college
At 1:34:25, how about throttling the DRAM access. It'll definitely reduce the hammerings and shall not meet the access rates for erroring out adjacent memory rows.
It's high time CMU waived off gre..2-3 months getting wasted for learning vocabulary.Stem courses can waive off so that they can concentrate on research papers or something constructive.Thank you
so even if the operating system schedules the two processes to two cores, which is fair because each process gets its own, but bottleneck is the memory access policy.
Memory Hog Problem (Solution, my thoughts): Considering the bottleneck is memory controller and I see the primary reason is the fetch logic is predefined and hard to control as a static parameter. What if we abstract the functions of the memory controller and leave them as API's to be implemented on the system software layer. What I mean is suppose we if we have an interface to implement scheduling logic, we can actually implement the memory access logic on the device driver of the controller and have the device point to this logic. This makes it more generic.
here www.archive.ece.cmu.edu/~ece447/s15/doku.php you can find all course related materials, in the prerequisites you'll find the list of related courses
colloredbrothers This is due to process variation effects. Cells are of different size and strength as manufacturing is imperfect. Simplifying a bit: Some cells can inherently store less charge than others (due to a small capacitor size) and some cells are inherently more prone to leaking faster (due to a weak transistor). A combination of less charge (small capacitor) and fast leakage (leaky transistor) leads to a fast-leaking cell. For more, see references [8, 21, 25] here: users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf and take a look at this paper that explains the charge storage and its effects on latency: users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf
+Carnegie Mellon Computer Architecture Wouldn't the access pattern (of the DRAM) influence the need for refresh more than PVT variations? Say a particular row is constantly written to - this row would not need regular stand-alone refreshes since the write action itself inherently refreshes data. I can think of similar analogies for read actions as well, influencing how regularly refreshing is needed for a particular row that is constantly read from. But I do believe that exploiting PVT variations can cause significant gains since I think memory is designed with a significantly larger guardband in comparison to logic thereby allowing more room for adaptively cutting into the guardband and extracting better energy/performance.
+Gokul Subramanian "More than" is very debatable. However, access pattern of course affects the need for refreshing a row. The example you gave for reads and writes makes sense. In fact, take a look at this "Smart Refresh" paper that proposes to exploit the fact that a recently accessed row does not need to be refreshed: dl.acm.org/citation.cfm?id=1331714. Usually, techniques to eliminate refreshes of recently accessed rows comes at a high hardware overhead needed to keep track of recently accessed rows, however, as explained in Section 4.2 here: users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf.
+Gokul Subramanian You are right that there is a large guardband in refresh and timing. Current DRAM refresh and timing parameters are set to ensure correct operation in worst-case devices and operating conditions. Exploiting the retention time and access latency heterogeneity of different rows and operating conditions can greatly improve the performance and power consumption of modern memories. I would recommend anyone interested in this topic (retention time and timing variations in modern DRAM) to read the following papers. "RAIDR: Retention-Aware Intelligent DRAM Refresh" users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms" users.ece.cmu.edu/~omutlu/pub/dram-retention-time-characterization_isca13.pdf "Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case" users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf You can find the presentations of these papers at users.ece.cmu.edu/~omutlu/projects.htm.
Potentially, but that solution is not only too expensive (a row buffer is huge), but couples the DRAM chip design (which contains the row buffers) to the number of cores (which is part of the CPU, GPU or accelerators). So, it is not a good solution.
2015 lectures are more recent and the recordings are likely to be better. So, they are more recommended. You can also check out more up-to-date versions of the course at @OnurMutluLectures Digital Design and Computer Architecture course from Spring 2020: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-AJBmIaUneB0.html Advanced Computer Architecture course from Fall 2020: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-c3mPdZA-Fmc.html
Question isn't their a problem with selecting rows and columns with a Mux, as if you were to activate multiple rows when activating a column you activate all values that have a row activated?
I am new in operating system. ****Does changing operating system have any effect on instruction set architecture or vice versa? Does operating system comes with its own assembler?****
Denial of memory service---does one row buffer per each core can serve the purpose?I mean for 2 cores 2 row buffers are need and in DRAM Memory controller we need to set equal priority for both the core requests. @Prof. Onur Mutlu
I like the levels of transformation but it doesn't include configuration errors or the OSI model. Many programs work on more then one system (client/server). How would you include those into your levels?
Is this the best self teaching way to learn Computer Architecture I really want to learn but its not my major and don't want to pay extra. Is there an MIT open courseware available. Any help would be appreciated thank you
