LMARV-1 reboot part 13: More sequencer schematicking 

Since MEPC and MCAUSE differ in only 2 Bits, you could use the last unused sector of the second chip for the other constant and replace the 3rd big chip with a single OR Gate to combine MEPC/MCAUSE_NUM_TO_CSR_NUM for the remaining similar bits.

The PC+4 can be implemented as +1 logic, because the lower 2 bits will never change. This makes me wonder if you could use a 30-bit latch+counter for this. Then of course you do need a clock signal to increment it once. I know this is not working 'combinatorically', but it might be worth to investigate.

Okay there has been people talking about the PC incrementer already here, but I just ended up thinking about how it actually only needs half-adders since it's only an incrementer, and decided to figure out how much it would be in "pure" logic (didn't figure out carry-lookahead yet, but just for curiosity, as a ripple carry...): Input An, output Yn, Carry Cn ^ is XOR, * is AND. Y0 = A0 ^ 1 C0 = A0 * 1 = A0 Y1 = A1 ^ C0 = A1 ^ A0 C1 = A1 * C0 = A1 * A0 2 XOR, 1 AND, delay 1 After the first 2 bits, it's just a sequence of half-adders: Y2 = A2 ^ C1 C2 = A2 * C1 Y3 = A3 ^ C2 C3 = A3 * C2 2 XOR, 2 AND, delay 2 So a 30-bit incrementer (bits 2 to 31) with ripple carry would be 30 XORs, 29 ANDs, 29 gate delays 5ns * 29 = 145 ns Which is less bad than I was expecting - I'm curious as to how much clocks your design has for INC_PC to work, didn't look into it yet but logically it could be most of a machine cycle? Wouldnt be that bad. From what i could find for 74LVC at mouser, that'd be these in chips: 8(*4G) 74LVC08A + 15(*2G) SN74LVC2G86 = 23 chips vs I think you were talking 11 big CPLDs? Also I'm starting to go "geeze this thing is gonna cost a lot only in chips" - obviously I know it's not supposed to be cheap lol, or you'd just use an FPGA ... or an emulator :P From the other suggestions, the counter sounds like a neat idea, though maybe complex to operate. Oh a final PS. As i was looking up the ATF1502s (in digikey it happened to be), the fastest 3.3V one (ASV) I found was 15ns (10ns for the 5V version).

This board is going to end up being the size of a pizza box! And as warm as one, too :)

Yay, I made a suggestion that got implemented! 😸 All pins will go hi-Z while programming, so that would very likely produce undefined behavior. I would recommend making use of the in-circuit programming function because it is sooooo convenient. You might just hold the reset button to stop the machine from functioning while the CPLDs are programmed, or perhaps, since the connector will have a few spare pins, maybe a custom programming cable that holds the machine in reset while it's plugged in? Another thing to be aware of with the naming of the TDI and TDO pins on the programmer is that TDI of the programmer should go to TDI of the first CPLD in the chain, and TDO to the TDO pin of the last CPLD. Completely reverse to what you might expect, but it caught me out.

Seems you forgot to add the csr_num_is_mtvec output to the main page

There is still a pretty good reason to use a CPLD instead of the ALUs to do PC+1 (the lower 2 bits are 0)... If you were doing this in an actual CPU, you would probably build a custom chip for this specific task. A typical adder is actually a 3-input adder (A,B, and carry in) and outputs the 2 bit result (result and carry out). However, for an incrementor, B is always zero, and the carry in for the chain is 1. So you really only need 2-input adders (i.e. a half adder). In terms of combining multiple functions in one chip, I'm not sure that would work, since you effectively need 30 inputs and 30 outputs, so 60 IO. Although, to be fair, if you were doing this without any CPLDs, you would probably just use the ALU adder itself for the PC increment and do the PC increment in one of the compute cycles (I believe the 6502 does that?). Also, for the crs_num_is_mtvec signal, you may want to put a buffer after the pullup resistor, in the event that it feeds to more than one chip (there's a lot of capacitive load on that wire already).

So for the INC_PC, how much time do you have for getting the result and how fast do you plan to clock it? As soon as the PC has new value then the adder starts calculating PC+4 so ideally you already have PC+4 calculated before you have next cycle which needs to increment the PC. Basicaly I am thinking if you really need a fast adder for incrementing the PC. If not you could maybe just use 8 4bit adders like 74AC283 in series, it has 16.5ns max propagation delay at 5V supply.

Probably a bit late to comment, but could the 4 bits you checked were positive (CSR_NUM0, 2, 8, 9) [at time 1:06:11] have been put through NOT gate and used with the other zero signals, saving you having the differing logic for the different sets of bits bits?

13:22 is the 10k resistor small enough such that it charges the input capacitance of the OR gate fast enough? Maybe you will have to swap it for a smaller one. And maybe the OR gate should be schmitt triggered if it is not already.

So the next logical step after this is a silicon version, right? ;-)

I wonder if you could fit all of the 74LS283 stuff in a single ATF1508?

22:05 - justify it by saying it's clock domain gating! The point of the signal is to entirely turn off this block's responsiveness to the clock. That's essentially the same thing as clock domain gating, except on a PCB with packaged gates. And you're not exactly running CTS on the other side. But other than that!

instead of 74ls181 you could use 74ls283, its smaller and probably faster