Low-Jitter CMOS Clock Distribution 

Prof. Tony Chan Carusone delivers a tutorial on the design of CMOS clock distribution circuits for low jitter. Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. In advanced nanoscale technologies, CMOS buffers (i.e. inverters) are increasingly being used for the distribution of multi-GHz clocks. This tutorial provides quantitative analyses of the main sources of jitter in CMOS clock distribution: power supply induced jitter, jitter generation, and jitter amplification.
Read all the details and cite this work via our open-access paper:
X. Mo, J. Wu, N. Wary and T. Chan Carusone, "Design Methodologies for Low-Jitter CMOS Clock Distribution," in IEEE Open Journal of the Solid-State Circuits Society, 2021. doi: 10.1109/OJSSCS.2021.3117930.
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