@@PhilsLab Hehe... They are, most definitely! Just imagine, I did my last PCB maybe 30 years ago with a sharpie, and nearly causing a chemical spill in my parent's backyard :) You are providing a level of expert details, that is hard to come by for an amateur like me. So yes, I will have to check my little project once more, before ordering prototypes. But who knows, maybe I should better wait for the next video before I do so... ;)
Excellent video as usual. Vias are at the heart of many manufacturability and reliability issues. During a course, our instructor mentioned this story. A company had issues with this military grade PCB having an intermittent issue that only happens in the field but not during lab testing. It turned out that some of their vias weren't sized properly for their intended environment. The via walls would crack due to thermal expansion after being exposed to the sun but as soon as the board cools down, the issue disappears.
@@PhilsLab No, the course was "Certified Printed Circuits Designer" from PCEA and taught by Mike Creeden. The two are friends so probably one of them heard it from the other.
seriously this guy is gifted. thank you Phil. great content as ever. If you mentioned back-drilling, microvia and etc. a bit then it would be a Bootcamp of vias :)
Well Phil, I am an amateur at most everything, but after watching your vids I am reminded I am a baby EE. I always learn something new. Thanks for all you do.
This is "grail" type info... the stuff you've always wanted to ask someone, but never did and never dug down to find the answer to. Thank you for this!
Absolutely brilliant as always Phil. Could you give any recommendations for other sources that continue on this topic and go into some of the further details you mentioned, please?
quick question, i know there isn't a 'standard via size' but since there isn't much current difference between them, what are the downsides of sticking to the smallest viable size ?
Great ideas and tips in all your videos!! Congratulations!! may be you could talk about the interconection between analog/digital ground planes with a net tie, resistor, ferrite...or with only one big plane for all....thanks for your videos!!!! :)
You're explenation on the stitching via equation is so well done, was the explenation from a book or you just figuring it out over time because most of the time we are given equations without proper explenations to what the components actually do either individually or in smaller groups. I think it would be quite a useful skill to have. I suppose one way I could of figured that out would be to keep an eye on the units when multiplying the different factors together to see if there is anything that stands out to me, since that is the only way I could see my self figuring this stuff out. Real cool video though thanks for sharing your knowlege
Hi Phil, just a quick question about the stitching vias for shielding. You mention "spacing the vias apart by L" and you give this nice drawing where L is the distance between the via centers. Is this correct, or should L be the distance between the outer points of two contiguous vias, since the radius of the vias might have effect?
Hi Ruben, As shown in the drawing, the distance should be measured from the via centers. The main 'via connection' is along the 'barrel' - not the pads. The pads typically will not extend down or be placed on inner layers (in Altium, the function 'removed unused pads' can be used).
To my understanding I do not see why this should increase PCB cost, but it can cause "solder wicking", where the via will drag the molten solder from the pad down into the hole and can cause bad joints as not enough solder is left to connect the pin to the pad.
Why do you need any annular ring on the top and bottom plane with transfer or stand alone stitching via? Making the hole size equal the pad size would allow the transfer via to be closer to the signal via and save routing space. The plating is in the hole and connects only to the inner ground planes. Is the annular ring required for the plating?
Isn't a GSSPSG layout is better for 6-layers PCB, than SGSPGS? Signal to power has a same return path as signal to ground. And considering a core between layers 2 and 3, and x3 thicker outer planes than inner ones.
Hi Phils Great content again as always of course :) I have a question about via impedance. To provide controlled impedance, Should we calculate via impedance ?
Thanks, Kadir. For most systems (unless you're working with several GHz++) it's not important - however, I try to minimise via usage on high-speed lines.
So my understanding is that any board of more than 2 layers cannot be manufactred by JLCPCB because they do not support blind vias! Am I right or am I missing something?
If a manufacturer offers via in pad as a standard option, why not take advantage of that option? The solder screen will need to be modified for the volume of solder wicked into the via, but that's not an insurmountable problem.
9:15 regardind differential pairs this may also be a very insightful video: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-QG0Apol-oj0.html ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-QG0Apol-oj0.html
Hi so practically you design 20 via’s (if the design permits) in a wavelength? This week I saw a video with Eric Bogatin (ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-kdCJxdR7L_I.htmlm35s) who advised to put at least 6 via’s in a wavelength. What’s your thought about that?
