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Resonance in RLC Circuits || Analog VLSI Mastery (Cohort 0-10) 

Himanshu Agarwal
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This course is helpful for Placements in Analog VLSI domain.
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8 сен 2024

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Комментарии : 11   
@user-dn7ep3gg8y
@user-dn7ep3gg8y 7 месяцев назад
Sir, how did you obtain Vmax/ root(3) for -3db level for parallel RLC after applying log? This differs from series RLC's 1/root(2) multiplier?
@HimanshuAgarwal_
@HimanshuAgarwal_ 7 месяцев назад
Written by mistake
@hardikjain-brb
@hardikjain-brb 2 месяца назад
Finally done with your challenging analog series , interview series and this rc rl series. My review is you teach very well and actually analyse things nicely ; I now have great intuition for RC ckts ; best wishes for this channel and my TI interview :) Thankyou
@charishmarongali4787
@charishmarongali4787 25 дней назад
Bro is this enough for analog placements
@hardikjain-brb
@hardikjain-brb 25 дней назад
@@charishmarongali4787 intern to mil gayi isse, legit best resource hai, inke rc ckt ke first lec se ques tha mere interview mai, to bhai soch kitna accha series hai pura
@nitinchinmay260
@nitinchinmay260 3 месяца назад
How did you infer that the areas cut by x and y in 36:09 are equal? Is that equal everytime?? And at 38:24 WL = 10^3-10^6/2 is not very low. Infact it's very high(considering the magnitude of the frequency) Can you please comment on this sir?
@HimanshuAgarwal_
@HimanshuAgarwal_ 3 месяца назад
1) Graph will be symmetric about Wo. 2) You can't take magnitude there.
@-MohammedShoiabMalik
@-MohammedShoiabMalik 7 месяцев назад
When will cohort 11-100 will come? Waiting for it please give update about it
@user-nl7og4sd3y
@user-nl7og4sd3y 7 месяцев назад
is RL or RLC circuit necessary for gate aspirants in ECE
@HimanshuAgarwal_
@HimanshuAgarwal_ 7 месяцев назад
Yes, it is
@SumitGupta-om4zn
@SumitGupta-om4zn 6 месяцев назад
Sir when cohort 11-100 will come please update as soon as possible 🙏🙏☺️☺️
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