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Опубликовано:

4 авг 2024

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Комментарии : 20

@HimanshuAgarwal_ 11 месяцев назад

Watch Anish taking my Mock Interview - ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-MdwLuhIkIYc.html Book Your mock Interview - topmate.io/himanshu_agarwal

@pawanpangapawan3341 11 месяцев назад

Couldn't reach through this link

@HimanshuAgarwal_ 11 месяцев назад

@@pawanpangapawan3341 Will work now

@SAGARsince-in7ek 11 месяцев назад

22.10 in Phase Plot the slope will remain constant till 5/RC and not till 1/RC and then the slope will be +45 till 10/RC ...and then zero slope till infinity.

@SAGARsince-in7ek 11 месяцев назад

this is very helpful! please give more intuitive videos like this!

@arjunnair6202 6 месяцев назад

For the MOSFET Source output question, the output would only be Vdd-Vth, if the Resistance R is strong enough to create a feedback such that Vo/Vi transfer function is a straight line, right? Otherwise |VGS| of the device would be higher than Vth, right?

@IcRDlayout 7 месяцев назад

Much appreciated sir 😊🫡 Wonderful questions,i like it 😊

@ebadurrahmankhan9033 11 месяцев назад

Mock interview is benifitial to all

@amazonindia9264 11 месяцев назад

Awesome

@champadas2301 9 месяцев назад

👍👍well done Anish ❤❤

@MhdAliAlashkar 7 месяцев назад

أحسنتم حياكم الله

@amanruke3961 11 месяцев назад

👍🏻👍🏻👍🏻👍🏻👍🏻

@ankitdogra9544 11 дней назад

where is your method to solve the thevenin prob ? can you share video link ?? 🙏🙏🙏

@amazonindia9264 11 месяцев назад

bring Soumya Kanta Rana mock interview in the next video please bro

@HimanshuAgarwal_ 11 месяцев назад

I can't interview him ! He is a living legend 🌟

@TheBhushan414 5 месяцев назад

Hi It was good interview. questions are good and thanks for posting it in RU-vid. At time stamp 46:05 really the gain at that node is 0 ? because you have current mirror load is there, if resistor or pmos load is present then that explanation is correct. But here we have current mirror. You can correct me if am wrong. Also procedure for calculating rout seems odd to me but answer is correct. while calculating left side nmos and pmos were not involved. In Razavi (second editionDesign of Analog CMOS Integrated Circuits by Behzad Razavi ) page numbers 152, 153, 154 have simple explanation of Rout calculation. Please correct me if I am wrong.