This section contains information on the following topics:
-|P|-: Scan operand for positive signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
The output rung will be set to “1”, when the input operand has the rising edge signal (From negative to positive transaction)
-|N|-: Scan operand for negative signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
The output rung will be set to “1”, when the input operand has the falling edge signal (From positive to negative transaction)
-(P)-: Set operand on positive signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
When the input state of the rung has the transaction for the negative to positive (“0” to “1”), then the Operand tag is set to “1” for one program cycle, in all other cases, the operand has the signal state “0”.
-(N)-: Set operand on negative signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
When the input state of the rung has the transaction for the positive to negative (“1” to “0”), then the Operand tag is set to “1” for one program cycle, in all other cases, the operand has the signal state “0”.
P_TRIG: Scan RLO for positive signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
The output of the rung set to the signal state “1” for the one program cycle when it detects the positive single edge at the input of the rung at the instruction. In all other cases, the output returns the signal state “0”.
N_TRIG: Scan RLO for negative signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
The output of the rung set to the signal state “1” for the one program cycle when it detects the negative single edge at the input of the rung at the instruction. In all other cases, the output returns the signal state “0”.
R_TRIG: Detect positive signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
This instruction, can detect a state change from “0” to “1” at the CLK input. If the instruction detects a state change at the CLK input from “0” to “1”, a positive signal edge is generated at the Q output, i.e., the output has the value TRUE or “1” for exactly one cycle. In all other cases, the signal state at the output of the instruction is “0”.
F_TRIG: Detect negative signal edge
Data type: BOOL
Memory area: I, Q, M, D, L
This instruction, can detect a state change from “1” to “0” at the CLK input. If the instruction detects a state change at the CLK input from “1” to “0”, a negative signal edge is generated at the Q output, i.e., the output has the value TRUE or “1” for exactly one cycle. In all other cases, the signal state at the output of the instruction is “0”.
4 май 2022
