Verilog in 2 hours [English] 

A really descriptive video on how to write verilog codes... Even a beginner like me was able to understand what lies in this intriguing topic in a single go!

Outstanding presentation. Never seen such a good projection of a topic.🙌

A topic at the core of digital circuit design, covered by an expert of the field.

Much needed short course. Thank you.

thanks sir. A clear and best video for Verilog and more

Thank you so much sir for this wonderful basic video which helps a lot for beginners like me

You did an amazing job brother.Jazakallah

Very impressive tutorial. Thank you for sharing this to us..

Sir kindly give 1 session on VHDL as well like if we know Verilog how we can do programming in VHDL as well. I tried to understand it but its bit different and there are some differences which I am not able to understand in perspective of Verilog. Like this session if you can give VHDL session as well it will be great. Thank you so much

Thanks for a great video. Was very useful for me!! If youll have more, it would be great. You are explaining very good. Maybe come more complex example. (In english)

paji tusi great ho, nice video. please make video in punjabi on Intel Altera FPGA also, thanks !!

A heartful thanks to ur work

May I please get this ppt, for teaching purpose? Thanks a lot.

Wow this was so helpful thank you so much

Thank You !!

Excellent video

Thank you so much 👏

Good lecture!!

Hi, thank you for the informative video! Would you be able to provide the entire code for the state machine please?

hello ! can you please provide me reference code for amba ahb lite protocol for my research purposes thanks !

At 8:30 , when the enable signal is on the rising edge, the output shouldn’t 4 also be coming as output? Or does the output starts in the falling edge of the enable signal?

your sound echo not very clear, do you use speaker phone?

Voice clarty is not good

Dear Sir Thank you very much for this helpful video Please, I try to write the following Verilog code in Vivado, the synthesis process is OK but when I want to implement it an error signal appear !! module Tog_not (hsync, EOL, q); input hsync, EOL; output reg q; always @ (posedge hsync) begin q

Okay but how do you download verilog? Where does it take place?

sir do you have sdr transmitter code

Please can you design a course on System Verilog and verification through it via UVM? It's not available fully anywhere and may help us a lot.

Bro mouth lo mouth lo matladukuntu evariki ayyiddi bro

Please get a better microphone!!!!

Omg bro can I buy you a mic ?

Resonud occured

I need professor number ,i want A2A class

not a good explanation