Xilinx Vivado to Design NOT, NAND, NOR Gates. 

his way of explaining is awesome ! the way he say's what to do step by step is so nice helps u learn in no time, one of the most under rated video 😤😤😤😤

very informative and very helpful! thank you so much!!

good initiative sir

The run simulation is giving not responding and asking to close the progress..... How to slove this...?

I am getting this error in vivado software "ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors."

how i generate verilog code using bloks like and,or gates etc..

sir what is the 11th video in this playlist? mistakenly added?

Tq sir

Not able to install vivado it install upto some initial stages then starts from 0 showing repeated download error how to install

sir my output is stuck at z dont care condition, i dont know why

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