Analog Circuit Design Engineer Interview _ Asymmetrical Op-amp analysis 

Thanks sir👍

This can be explained in this way, As M2 size doubled, still M1 and M2 see same vgs-vth as source and gate are same for both.So if same current is assumed in both nmos, M2 drain should go lower compared to that of M1. As M2 drain goes low, it goes to triode first. In your Id equation you didnt consider vds dependency.if it was taken it is easily explainable. I assume common gate of M2 explanation is not correct. Then it applies for M1 also and it contradicts out node goin low

i have a doubt that as source voltage is increasing then how the current is still Io/2 in M2??? one more doubt that for defining regions of operation we consider large signal/DC analysis then why u have taken ac analysis to find the regions of operation of the transistors?

Thank you so much sir ❤❤❤

what will happen if PMOS current mirror is replaced by something else. in that case will the dominant path analysis hold good?

What if M1 Vbias is twice of M2 is it still the same current flows through M1 M2.What are the currents and voltages if we sweep Vbias of M1 keeping M2 Constant?

Why will the M1 drain increase when the source is increasing?

simply M1 go to triode because 2I/3 Flow through that M1 and M3 I/3. v node will discharge.

what is this if the vo node going down how M3 will reach in triode. Completely wrong explanation.

your voice is so low, please buy a cheap external usb microphone from chinese websites

Your analysis is completely wrong