* Analog IC Design Engineer. * Ex-Research and Development Engineer (Analog Circuits). *GATE'23 EC Qualified.
*** For paid Analog Circuit Design Course and Guidance you can fill the G-form: forms.gle/JQZa5TNiuBBg8Hej7
*** I have Completed my degree, Bachelor of Engineering (BE) in Electronics and Telecommunication Engineering (ETCE) from "Jadavpur University", Kolkata, India in 2023.
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Explained very clearly Sir 😊 So this is ah! And a very interesting first-level differential pair uses a current mirror circuit as biasing and adds a negative feedback (R/2R) and uses CL as a compensation design circuit🤔 Use TSMC .18 process for the Circuit and tape out the ? Ic
Thank you Sir 😊 It looks like Diffential pair using diode connected loads .. and the solved CM ,DM 🤔 vo/vd=-gm1(R//ro1//ro3) , neglected CLM So -gm1*R....Answer
What if we apply test voltage Vt with current It from Zin And apply nodal equation in input side of buffer... Output of buffer will give -2Vt and current flowing into buffer will be 0 since ideal.. (Vt-(-2Vt))Cs= It so Vt/It=1/3Cs...
Very good explanation😊 Simple conpect with very interesting c potental suddenly or abruptly because the current..the vin=5u(t) and then from to Rc2 from 2.5v charge close to 5v and Rc1 discharge from 2.5v exponential decrease to 0 wavefrom...
Thank you Sir 😊 Cs feedback circuit with rds finity and then gmro>>1 ,So Rout=vt/it,it=gmvgs+gdsvds=gmvt+(1/rds)vt, vt/it=1/[(1/gm)+rds] So vt/it=(1/gm)//rds ...Answer
Thank you Sir 😊 f=0,current source open wp=1/req*ceq=1/11*(1/2π)=0.57 rad/sec vo short wz=1/1*(1/2π)=6.28 rad/sec dc gain vo=I *(10//1),vo/I=0.909 approximately vo/I=1 So dc gain A db=20log|A|=0 db The final Bode plot choice is D Please let me know if you have any misconceptions, thank you
Thank you sir 😊 (vo-vin)/R+(gmpvin)+(vo/rop)+(gmnvin)+(vo/ron)=0...(1) (vo-vin)/R+vo/(1/(rop//ron))+gmpvin+gmnvin=0.....(1) vo(1/R+(1/ron//rop)=(vin/R)-gmnvin-gmpvin=0...(1) vo/vin=((1/R)-gmn-gmp))/(1/R)+(1/ron//rop)....(1) If R infinity vo/vi=-(gmn+gmp)/(1/ron//rop)=-(gmn+gmp)*(ron//rop)...Answer R=0 vo/vi=infinity/infinity=1...Answer
@@AmitBar-Analog_Circuitsopamp is saturated but towards Vss i.e 0v as the answer you found is not satisfying +ve f/b where v+ should be greater than V- but your v+ is coming less than v- which means+15v is not correct. If u keep o/p 0v and then calculate v+ and v- then u will get corrected results
- ve feedback (my explanation) pls tell either it is correct or not. As it is PMOS common source, so If we increase Vg of pmos then Vgs will decrease as a result current will also reduce so IR drop reduced (my r is fixed) , means Vo will reduce. So negative feedback .
