STMicroelectronics Analog Design Engineer Interview _Plot node voltages wrt Rd

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I forget to mention one things,
fist check mos is on/sat. or not by open circuit test.
Then check the negative feedback.
LDO circuit analysis.
**
Analog Design Interview/Screening Test questions for Texas Instrument ,Micron Technology, ST Microelectronics, Synopsys, Steradian semiconductor, NXP Semiconductor, Analog Devices, Intel, Samsung etc.
draw the node voltages .
#mosfet
#nodevoltage
#plotvoltagewaveform
#texasinstruments
#analogdesign
#analog_circuits
*You can join our Telegram group for solve your doubts/get prep materials/discussion-
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All important interview question-
*Analog Design Engineer Interview Question:
• Find small signal Vo f...
*You can connect with me on LinkedIn- / amitbarju2023

Опубликовано:

9 мар 2024

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Комментарии : 18

@EnlightenedJourney1012 4 месяца назад

In the end, you talked about large signal analysis... What will be the case if we consider small signal analysis in this question

@AmitBar-Analog_Circuits 4 месяца назад

There is not present any small signal Vin or so

@PSPS437 4 месяца назад

Great video Amit Sir

@pablomarco5118 4 месяца назад

many thanks

@zinhaboussi 4 месяца назад

Good video, the only problem is that your English is not understandable sometimes

@qemmm11 4 месяца назад

Thank you

@ROCKPWINCE 4 месяца назад

bro , you said Ron is zero which means even with VDS = zero , the MOS can sustain a current in Triode region

@ROCKPWINCE 4 месяца назад

Hi, I jsut wanted to check on this - that when you keep increasing RD , the gate voltage will keep increasing to keep the Mos in saturation . Therefore the Mosfet will go into linear much before 4k ohm value . Secondly when the circuit does enter linear , VDS=0 , how are you opencircuiting the circuit , becuase the Gate voltage will go to Vsat =5v and drain is at 5v nad source is at 0V ?

@AmitBar-Analog_Circuits 4 месяца назад

Current constant means VGS is fixed ,here Vs is already fixed due to virtual short so Vg is also fixed while increasing Rd .. okay?? If Vds = 0 ,then current is zero so mos off not in liner region ..hope ,get it

@sumanbaur3021 Месяц назад

I have the same doubt

@dolankundu2537 4 месяца назад

How current is zero when vds =0 . We know when vgs is less than threshold then only current should be zero. Can you please explain this why ?

@AmitBar-Analog_Circuits 4 месяца назад

Go and spend some time for mos basics ,you can follow Dr Razavi sir lectures on RU-vid free

@AmitBar-Analog_Circuits 4 месяца назад

You have a element ,across it the voltage difference is zero,,so can any current flow through that element?? And current can be zero in 2 conditions for mos,,check it by yourself..Thanks

@VivekKumar-gi5rv 4 месяца назад

just discovered this beautiful channel ......one doubt sir.....Had the op-amp been non-ideal..... how to approach those questions? In that case if Igate is 0 of mosfet, then Vp of amp must be equal to Vn....cause Rout is not zero and also the A is given to be finite.....Am i correct? Sir please guide me....

@VivekKumar-gi5rv 4 месяца назад

Plz help guys....

@Harsh-1603 4 месяца назад

Hello sir i will be joining mtech this year , and interested in analog profile , please tell the sources to follow from basic .

@AmitBar-Analog_Circuits 4 месяца назад

Already have a complete road map video in this channel,plz check once

@yavuzkilic1223 День назад

great work, however too repetitive! you could probably first record and play back and see how much repetition you have, and perhaps then cut back on that which might mean the length of your video will be third and far better!