This video is based on the Samsung designing post interview. Here we have just discussed 2 questions. Please give your honest feedback in the comment sections.
For the second question, when MOS is in saturation it acts as a constant current source, Ic=Cdv/dt, the dv/dt will be a constant slope m=Ic/C, your graph will have a linear behavior and then will go down close to zero
Yes, we are neglecting CLM. there are many assumptions made here. for example we are also ignoring the anti parallel diode between drain to source which will clamp any negative voltage across MOS to -0.6V. so -2V is never possible in the first place.
But, MOS is never in SAT, because VGS - VTH = 3-0.3 = 2.7V, Drain voltage jumps from -2V to 1V at t = 0...So, For t > 0 , Vds < Vdsat, MOS is in triode...is my understanding correct? did i miss anything
R_linear won't vary with VDS ideally, you can easily find it out from from Id Vs Vds characteristics. (for first question) for the second question , when transistor is in saturation , ID won't be the function of Vx, therefore Vx= 5-ID*(t/C) is a linear curve after that exponential discharge continue. Compare the discharge of Vx in question (2) to inverter output where NMOS initially in saturation after that it is in saturation.
Q1: For a REAL NMOS with body diode, the capacitor CANNOT start at -2V, if the voltage source starts at 0V. The body diode would allow a max voltage ~ 0.7v. You should draw the voltages before t=0. If I were the interviewer, I would ask to see that.
And please tell me what are the important areas that I need to prepare for analog profile(especially written test ) . First tell about written test . Please
When we apply 3v I/p, the capacitor charges with a time constant of Ron*C. When it charged to 3v ,then Vds=Vx=0;----->Nmos drain current =0. So, Vx settled(clamped) at 0.(bcoz no more charging path(open circuit) after Vx=0. I think ,this way is also fine right ?
Sir first of all thank you to the content .Sir you explained in a good way .but I am requesting you plz make vedios on following type of cases 1) when a capacitor is connected at drain side of mos and pulse signal with some time period T applied what can be the output signal,how capacitor voltage varies 2) When cap is connected at source and pulse signal applied with time period T what can be the output signal,how capacitor voltage varies. 3) when caps are connected at drain gate and different signals like step ,pulse with time period T is applied how cap voltage changes All these cases for pmos and nmos . These kind of things are not present in books. In the interviews and in the written tests these kind of questions they are asking if you make a vedio on this it would be a great help for us After this when caps are connected to cmos inverters of different combinations I.e at Gate,source,drain ,gate and source ,source and drain ,gate and drain ,gate and source and drain and applying different inputs like step,ramp,pulse and observing how cap voltage varies and what will be the output signal in each case . As a subscriber I am requesting you make vedios on this topic . One vedio it will take 45 min time
Thanks for all the advices. Gone through them thoroughly. So...I generally discuss those questions which I am quite sure of. So if I come around such question and I am quite confident of that will surely discuss that. :)
why Vx was 1v at the beginning like I never heart about capacitor subtract the voltage , I heart that when voltage meet the positive terminal they will add together like the circuit of clamper , can you please explain why 1v ?
In 2nd one, when it is in saturation, output impedance of Nmos is high. So, Time constant is high (RDS*C). takes lot of time to reach 2.7v(edge of sat). So, slope is less(almost flat to x-axis). When Vx falls below 2.7( triode region)-- Ron is less,so less Time Constant. So, Vx falls to zero at faster rate . So, high slope is there for Vx
In saturation region it will also be acting as a constant current source. So we can't just compare it with High Pass Filter Circuit. Because of constant current through the capacitor the voltage drop across it will be linear in nature. So.....
Sir.. When voltage across cap is 3v then at +ve terminal we take+3v then at negative terminal -3 then potential difference across the cap is 6v..please clarify thiss sir...
So the thing is, Firstly go through basic N/W Bachelor's level. Then you need to be good in Analog too. After that also, still u have to spend time discussing it with your friends and then also you might be ending upon a wrong soln so it's a bit tough 😅😆, but keep discussing such type of questions sooner or later you will develop a kind of understanding. Prerequisites 1. Gate questions EE and EC 2. Behzad Razavi 3. Nagendra Krishnapura lectures.
Sir I'm ee 2nd year student from grade b college of bihar (government college) So please tell me how to prepare for analog design engineer wheather Texas instruments or samsung and so on And do these companies hire from grade b college
