Cheng Wang, Flex Logix's senior vice president of engineering, talks with Semiconductor Engineering about how to use lookup tables in embedded FPGAs and what number of inputs is best for different applications.
www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01003.pdf For anybody interested, this is a great reference paper attached in the link above regarding LUTs and the trade offs. What I really wanted to know was the kinds of numbers that we can expect from propagation delays through a lut. And how LUTs are really constructed at the transistor level and how different companies designed theirs differently (haha no body is ever going to tell me that I suppose)
I mean, a LUT is really just a 1 bit prom with a, in this case, 4 bit address. All PROMs are LUTS, you can add them in parallel to add output bits, and larger cells for more input bits.
The problem that Mr Wang has proposed, is to build a LUT for 6 inputs using 4 input units. In his simplified drawing he drew only 3 inputs for the general circuit of 4 inputs. Then he shows why 3 general purpose 4 input circuits would be necessary to build a 6 input LUT.
@@doctoroctos You mean its actually a 4 input LUTs but he is only using 3 input so he draws only 3? As I can see that he had draw the 4 input LUTs correctly in behind when he wants to make a 12
