Nandland Go Board Project 2 - The Look-Up Table (LUT)

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The second Nandland Go Board Project. Learn about one of the two most fundamental components inside an FPGA: The Look-Up Table (LUT). LUTs are used to perform all Boolean algebra inside your FPGA development board. LUTs implement truth tables. This project asks you to light up an LED only when BOTH Switch 1 and Switch 2 are pressed down at the same time. This requires an AND gate.
For the text version of this video: www.nandland.com/goboard/look...
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24 мар 2016

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Комментарии : 31

@MrI7asson 5 лет назад

Thank you so much. I have watched several of your videos and they've been very helpful. You've explained things very clearly and made them look easy.

@Hfgh564 3 года назад

Amazing lessons, going to buy your board tomorrow!

@Aemilindore 5 лет назад

Thanks so much for this series.

@dexterz3 7 лет назад

What are the orange wires for? They are connected to the pins on the right side of the board. 13:30

@b213videoz 5 месяцев назад

9:44 ; does not terminate but separates,if it's the final entity there is no separator needed - like in Pascal Vs C

@ibrahimalnafisi432 4 года назад

How Can I show The RTL Schismatic? Thanks.

@Cali101Now 4 года назад

Can you please help me how disable the other two LED lights, i followed your feedback to others of disabling the unused i/o in the tools options bitmap tab, but it hasnt changed

@Nandland 4 года назад

You can create signals for those LEDs and just wire them to turn them off. Just make sure those signals match signal names in your PCF file

@stevebarsky 5 лет назад

I just received my Go Board and have been trying all evening to make this work. I've tried both the Verilog and VHD versions, both of which go through the synth/p&r with no probs. I'm able to program the board, no prob. I've double checked the constraint file. But all I get on the board is D1, D3, and D4 are lit at about 20% and D2 is lit at about 100%. The only hitch I had in the entire process is the Micron M25P10A was not an available choice, so I used M25P10, which I don't think is the problem since the board verified okay. What might be the problem?

@Nandland 5 лет назад

Sorry you're having difficulty! Usually that happens when the Place & Route constraint file is not correct. Double check that you have the .pcf file included in your project. Also double check that the signals at the top level entity match the signals in your constraint file. Good luck!

@stevebarsky 5 лет назад

I was too tired to read through the generated report and so I missed what was causing the problem. Maybe I was expecting the tools to throw up a big red flag and stop me from moving forward, but hey, this is a new world for me. Anyway, apparently this is one of those persnikity tools that wants mr to ACTUALLY select the CORRECT pin package! Thanks for the quick response - everything is hunky and dory now and I look forward to continuing in my education. Cheers!

@adambynes 8 лет назад

Dear sir, very good tutorial for the beginner but i have some questions below U said so much about the gates AND OR NADN NOR etc, but from the high level progamming languge VHDL verilog, we don't need to consider the gate things, even you can see the LUT usage in the synthesis. so each LUT can handle what kind of logical? LUT contains how much gates? do we have some ways to define the real LUT used in the FPGA, not just the logcial expression in VHDL? just like assembly for C.

@Nandland 8 лет назад

A 4-input LUT doesn't contain any "type" of gate. It contains all possible truth table combinations given 4-inputs and 1-output. It can be anything. To answer your second question, generally you're right, the high-level languages handle all of this stuff for you. If you wanted to get down to the "assembly" level for LUTs, you would need to look at something like project IceStorm (www.clifford.at/icestorm/) which reverse engineers FPGAs. Note that the Lattice FPGA they use is the same one on the Go Board.

@kssmyw 3 года назад

Hi! I have followed the tutorial but after I program the board, all the LEDs are constantly on but not full brightness and they do not respond to me pressing the buttons. I have tried both code files and reprogrammed the board multiples times, doesn't seem to make a difference. Can someone point out what I am missing?

@kssmyw 3 года назад

of course the problem was forgetting the pin constraints file. added that to the project and went through the rest of the workflow and the and gate works now. I do have another question: the other three LEDs are still always faintly glowing. I would like to clear the board so that it's back in its unused state (hoping this will stop the faint glow from the other LEDs). Does someone know how to do this?

@Nandland 3 года назад

@@kssmyw In iCEcube2: Tool -> Tool Options -> Bitmap -> Check the box that says "Set all unuused IO no pullup". Or you can explicitly set the LEDs to 0 in the Verilog/VHDL code. Or you can just ignore the faint glow :)

@kssmyw 3 года назад

@@Nandland worked like a dream Russell, thanks! really enjoying working through the tutorials so far

@xmotoFF 7 лет назад

I had a funny behavior when I compile this example with the iceproject tools. LED_1 worked fine, but for some reason the other leds were dimly lighted in the board. Anyways, I solved this problem by adding the these leds to the verilog code, and assigning them to 0.

@Nandland 7 лет назад

Yup that's one way to do it. Another way is to go into iCEcube2 and click on Tool -> Tool Options. Then on the Bitmap tab check the "Set all unused IO no pullup" box. The dim LED is caused by the pullup on the FPGA defaulting to ON.

@wilw3498 Год назад

Sir do you have an email that I can contact? I want to learn verilog with your guidance and one day be a good ASIC/FPGA engineer, I'm from a country that doesn't have these kind of stuff available for us to use.

@fernandoschuindt1665 6 лет назад

Put this into your ~/.emacs.d/init.el file: (setq ring-bell-function 'ignore) Thanks.

@Nandland 6 лет назад

lol, sorry.

@fernandoschuindt1665 6 лет назад

Hey, it was supposed to be funny, no need for sorry. :) Also, great material. You made me interested in FPGA and Verilog again.

@Nandland 6 лет назад

@phillipneal8194 5 лет назад

Hmmm. I just did project 1 and 2. But leds 2, 3, 4 still glow. Not strongly. But they are on

@Nandland 5 лет назад

Yes. There's a reason! I'll give you a clue it's in iCEcube2, there's a setting you can change to turn them off... Let me know if you want abother hint...

@phillipneal8194 5 лет назад

Ahh, but I am running on a Mac so I have to use the Yosys/Arachne-pnr/icepack/iceprog route. Internal to the code I assign i_LED2 = 1'b0 for all the unused leds. Can I assign a default in the constraints file ?

@Nandland 5 лет назад

@@phillipneal8194 Ah interesting. I'm not sure where the setting is in those tools, but there's a way to disable the pull-up on unused outputs. That's what's causing them to glow like that. It's fine to just leave them. Or you can turn them off in your code. I think it should be o_LED2 though to match the constraint file.