When i try to solve the small signal gain around the switching threshold, i get the small siganl gain is {-(gmn+gmp)*{1-[1/(R*(gmn+gmp))]}}/(G+gmn+gmp)...If (gmn+gmp)*R < 1 , then this acts as a buffer otherwise as inverter...is my analysis correct ?
Hi, request you to kindly upload videos on a regular basis . It could be tremendously helpful for interview candidates. All the very best & thanks for helping a larger audience out there . #skyisthelimit
Its basically PWM modulation on a second order LPF, if the duty cycle is 50% then answer is half of vdd which is 2.5. If you change the duty cycle, then output will change accordingly
Why not add two switches,one is above capacitor 1f and the other is above 10f capacitor??😊 Time is t1 and t2😊 First t1 closed and then or First t2 closed and then ....
Why in the negative cycle of input the out is not starting from - V. They all are parallel voltage should be equal. Why are sharing it between two cap.
So as discussed in the video make an R and C model of the circuit. If the R charging and discharging is same then Yes. Clearly here the circuit gets changes so it should not be the case.
Adding the capacitor makes the output voltage stable. The more the capacitor the more stable will be the voltage. In real designs as well we put dynamic capacitors inorder that our circuit just not start reacting to small noises and all. Would suggest you to see RC Network questions discussed here in the channel.
A CMOS inverter with resistive feedback where transistors are self-biased in strong inversion is designed and optimized for low NF and high IIP3 in LNA
what i can think is that since no current flows inside the mosfet so output is shorted to input and both the mos comes in sat as vds= vgs which results in vout = vdd/2 as per inverter characterstics .
Hi there thanks for the videos! Keep em coming! Just out of curiosity, may I know why the discharge and charging time constants are not equal initially?
Here if R tends to infinite then there will be no feedback, if R has some finite value then the circuit will acts as a negative feedback circuit. If we set the input to 0 and break the loop and increase the voltage by some +ve amount then NMOS will be on and PMOS will be off. So as it is a CS amplifier ckt then there will be 180 degree phase shift in the op, so for increase in input output decrease , so it is a negative feedback ckt, for finite value of R. Am i right bhaiya?
Bhaiya could you please make a video of buffer related questions, like calculation of 3 dB frequency, or kindly refer any resources from where I can practice this kind of problems.
your analysis is right actually but just think about this- the feedback is the one which effects the input ( alter it change it) but in this case it is not possible since we have a forced input. This kind of feedback os called feed forward feedback.
I have some questions. What is the effect of rise/false time of input on transient response? When can CGD be ignored? The resistor will be a feedforward path, not a feedback path if the voltage source is ideal.
Hii, so if your input is having a higher rise time or fall time then depending on the values of load capacitor, R and Ron( p or n) the output will get time to settle down to its final value ( which could be deduced by the formula mentioned in the video ). If the time constant is lower it will follow the input else will slow it down. If you have steep input with lower rise and fall time then also again depending on the loading it will follow or slow down the input. Now this question gets better if we have clock as an input to it then if the loading is higher and the input steep in nature than probably this will result in lower voltage swings at the output. Yep, you are right that this can’t be stated as a feedback until we have a forced supply at its input. Kudos on that🎉.
@@mrx1167 feedback is given directly to the input but since input is an ideal source so it won't be possible for it to be changed but this feedback is also connected to the output which is not tied to any ideal source hence known as feedforward not feedback ^_^
I think the discharge and charging current are different so in negative half cycle the Vx will be less than 0.5 volts Please correct me if I am wrong !!
