@ 8:30 I have said the black wavefoem to be the input which clearly is by mistake. As stated in the video, the input is varying from Vp and 0 as a pulse.
Why in the negative cycle of input the out is not starting from - V. They all are parallel voltage should be equal. Why are sharing it between two cap.
in last part of video; it says when input is zero initially it will got -v/2 ; bt according to me it should go -V becasue both cap connected in parallel ; correct me if i am missing something?
No it should be -V/2 as the capacitor will instantly divide the charge among themselves as the charge should be conserved after that then it will discharge through R.
@@praveenkumarmaddeti6668 yeah, but the pulse input one time period is a square wave right!.. That's is what being analysed over here. The same output will be repeated for all the cycles.
@@praveenkumarmaddeti6668 please see the last part where the two capacitor comes in parallel. They will come parallel only if input voltage is zero right!
Bro im having a small doubt. At t=0 the moment when applying sudden change in voltage 0-V volts the capacitors will be short circuited and the voltage at the second cap i.e,.will be zero right(in waveform at t=0,Vout=0)..But why V/2..can u clear it.
For the voltage of a capacitor to jump we need infinite current. At t=0+ infinite amount of current flowing through the capacitors. Here the value of both the capacitor is same. If we apply voltage division rule of the capacitor then the voltage across each capacitor will be V/2 at t=0+.
Hi, Thanks for the review. I had a question about the Vout(t=INF).. Will it be equal to 0 because capacitor discharging into C1 (the first capacitor) or will it be a capacitive divider like in your previous video .. in this case since C's are equal Vout(t=INF) = Vin/2 ? Appreciate your help. You are a great teacher.
@@arslanbhatti9771 at steady state the capacitor connected to source will block the current. This means that the drop across the resistor , 'R' will drop to 0 i.e. Vout will drop to 0
@@arslanbhatti9771 at t=infinity means at steady state omega=0 for a step voltage Capacitor will behave as a Open Circuit C1=C itself and in C2 || R the Resistor will dominant here since capacitor is at open ckt so o/p terminal equal to 0. As C2 has discharged all its voltage across R terminal and C1 has hold its voltage.
